In this paper, we present an efficient yet accurate inductance extraction methodology. We first show that without loss of accuracy, the extraction problem of n traces can be reduced to a number of one-trace and two-trace subproblems. We then solve one-trace and two-trace subproblems via a tablebased approach. The table-based inductance model has been integrated with a statistically-based RC model generation [l] to generate RLC models for on-chip interconnects. Application examples show that our method is efficient enough to be used during iterative procedures of interconnect simulation and layout optimization.[.
INTRODUCTIONIt has been shown for years that interconnect delay and crosstalk have become bottle necks in determining circuit performance. In order to simulate and optimize on-chip interconnects, the parasitic parameters (resistance, capacitance and inductance) need to be extracted from the interconnect geometry. This extraction nnust be accurate as a correlation with "final" verification engjnes is needed for design convergence. The extraction must also be efficient, because it may be performed dozens of times on the full-chip level and thousands of times on critical nets. Clearly, numerical extraction is hard to support during iterative procedures of simulation and optimization.Accurate and efficient extractions for resistance and capacitance have been achieved recently. For example, a 2.5D capacitance extraction methodology was shipped with Cadence Silicon Ensemble 5.0 product[2], and a fast generation of statistically-based worst-case RC models was implemented and used at Hewlett-Packard [I]. Both used the tablebased approach, which is suitable for iterative simulation and opt&ization purposes. Due to increasingly wider and longer wire traces, faster clock frequencies and shorter rising times, inductance effects of on-chip interconnects no longer can be ignored. However, no1 inductance extraction methodology, which is accurate and efficient for iterative simulation and optimization purposes, has been presented.In this paper, we describe an efficient and accurate methodology to extract inductance under the PEEC model. In section II, we validate two foundations which allow us to reduce the problem size of inductance extraction without loss of accu-1. Lei He is a PhD candidate at UCLA, Computer Science Dept..He worked with HP labs during 1998 summer and fall. Address comments to helei@cs.ucla.edu and nchang@hpI.hp.com racy. In section 111, we propose a table-based inductance extraction methodology based on the two foundations. In section IV, we present two applications of the inductaince extraction methodology: (i) to derive the effective (loop) inductance for a coplanar-waveguide; (ii) to be integrated with the statistically-based RC model generation in [l] to generate RLC models for onchip interconnects. We also use the RLC model to optimize bus structures. Section V concludes this paper.
Foundations for Inductance Extraction
A. PreliminariesThere are multiple metal layers in a VLSI technology. We assu...
This paper presents a heuristic approach to the optimal selection of standard cells in VLSI circuit design. We are considering a cell library composed of several templates (3-5) for each type of cell. These templates differ in area, driving capabilities, intrinsic delay, and capacitive loading. When realizing a logically synthesized circuit, we select the best templates from the cell library to minimize the total area of the cells under delay constraints.We have found a very successful heuristic approach to attack this discrete optimization problem. Experimental results show that this approach runs very fast, with the complexity of O(n'), and improves the results obtained from the technology mapping of misI1. [15]
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