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Switches today provide a small menu of scheduling algorithms. While we can tweak scheduling parameters, we cannot modify algorithmic logic, or add a completely new algorithm, after the switch has been designed. This paper presents a design for a programmable packet scheduler, which allows scheduling algorithms-potentially algorithms that are unknown today-to be programmed into a switch without requiring hardware redesign.Our design uses the property that scheduling algorithms make two decisions: in what order to schedule packets and when to schedule them. Further, we observe that in many scheduling algorithms, definitive decisions on these two questions can be made when packets are enqueued. We use these observations to build a programmable scheduler using a single abstraction: the push-in first-out queue (PIFO), a priority queue that maintains the scheduling order or time.We show that a PIFO-based scheduler lets us program a wide variety of scheduling algorithms. We present a hardware design for this scheduler for a 64-port 10 Gbit/s sharedmemory (output-queued) switch. Our design costs an additional 4% in chip area. In return, it lets us program many sophisticated algorithms, such as a 5-level hierarchical scheduler with programmable decisions at each level.

The load-balanced switch architecture is a promising way to scale router capacity. It requires no centralized sched-uler, requires no memory operating faster than the line-rate, and can be built using a fixed, optical mesh. In a recent paper we explained how to prevent packet mis-sequencing and provide 100% throughput for all traffic patterns, and described the design of a 100Tb/s router using technology available within three years. But there is one major problem with the load-balanced switch that makes the basic mesh architecture impractical: Because the optical mesh must be uniform, the switch does not work when one or more linecards is missing or has failed. Instead we can use a passive optical switch architecture with MEMS switches that are reconfigured only when linecards are added and deleted, allowing the router to function when any subset of linecards is present and working. In this paper we derive an expression for the number of MEMS switches that are needed, and describe an algorithm to configure them. We prove that the algorithm will always find a correct configuration in polynomial time, and show examples of its running time. I. BACKGROUND Our goal is to identify router architectures with predictable throughput and scalable capacity. At the same time, we would like to identify architectures in which optical technology (for example optical switches and wavelength division multiplex-ing) can be used inside the router to increase capacity by reducing power consumption. In a previous paper [1] we explained how to build a 100Tb/s Internet router with a single-rack switch fabric built from essentially zero-power passive optics, but without sacrificing throughput guarantees. Compared to routers available today, this is approximately 40 times more switching capacity than can be put in a single rack, with throughput guarantees that no commercial router can match today. The key to the scalabil-ity is the use of the load-balanced switch, first described by C-S. Chang et al. in [2]. In [1] we extended the basic architecture so that it has provably 100% throughput for any traffic pattern, and doesn't mis-sequence packets. It is scalable, has no central scheduler, is amenable to optics, and can simplify the switch fabric by replacing a frequently scheduled and re-configured switch with a single, fixed, passive mesh of WDM channels. Linecard Linecard Linecard 1 2 3 4 Fig. 1. Load-balanced router architecture A load-balanced router based on an optical mesh is shown in Figure 1. Figure 1(a) shows the basic mesh architecture with N = 4 linecards interconnected by 2N 2 links. Each linecard in the first stage is connected to each linecard in the center stage by a channel at rate R/N , where R is the linerate and N is the number of linecards. Likewise, each linecard in the center stage is connected to each linecard in the final stage by a channel at rate R/N. Essentially, the architecture consists of a single stage of buffers sandwiched by two identical stages of switching. The buffer at each center stage linecard input...

-The Internet is facing two problems simultaneously: there is a need for a faster switching/routing infrastructure, and a need to introduce guaranteed qualities of service (QoS

We present dRMT (disaggregated Reconfigurable Match-Action Table ), a new architecture for programmable switches. dRMT overcomes two important restrictions of RMT, the predominant pipelinebased architecture for programmable switches: (1) table memory is local to an RMT pipeline stage, implying that memory not used by one stage cannot be reclaimed by another, and (2) RMT is hardwired to always sequentially execute matches followed by actions as packets traverse pipeline stages. We show that these restrictions make it difficult to execute programs efficiently on RMT.dRMT resolves both issues by disaggregating the memory and compute resources of a programmable switch. Specifically, dRMT moves table memories out of pipeline stages and into a centralized pool that is accessible through a crossbar. In addition, dRMT replaces RMT's pipeline stages with a cluster of processors that can execute match and action operations in any order.We show how to schedule a P4 program on dRMT at compile time to guarantee deterministic throughput and latency. We also present a hardware design for dRMT and analyze its feasibility and chip area. Our results show that dRMT can run programs at line rate with fewer processors compared to RMT, and avoids performance cliffs when there are not enough processors to run a program at line rate. dRMT's hardware design incurs a modest increase in chip area relative to RMT, mainly due to the crossbar.

Switches today provide a small set of scheduling algorithms. While we can tweak scheduling parameters, we cannot modify algorithmic logic, or add a completely new algorithm, after the switch has been designed. This paper presents a design for a programmable packet scheduler, which allows scheduling algorithms-potentially algorithms that are unknown today-to be programmed into a switch without requiring hardware redesign.Our design builds on the observation that scheduling algorithms make two decisions: in what order to schedule packets and when to schedule them. Further, in many scheduling algorithms these decisions can be made when packets are enqueued. We leverage this observation to build a programmable scheduler using a single abstraction: the push-in first-out queue (PIFO), a priority queue that maintains the scheduling order and time for such algorithms.We show that a programmable scheduler using PIFOs lets us program a wide variety of scheduling algorithms. We present a detailed hardware design for this scheduler for a 64-port 10 Gbit/s shared-memory switch with <4% chip area overhead on a 16-nm standard-cell library. Our design lets us program many sophisticated algorithms, such as a 5-level hierarchical scheduler with programmable scheduling algorithms at each level.

-The Internet is facing two problems simultaneously: there is a need for a faster switching/routing infrastructure, and a need to introduce guaranteed qualities of service (QoS