Proceedings of the 2016 ACM SIGCOMM Conference 2016
DOI: 10.1145/2934872.2934899
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Programmable Packet Scheduling at Line Rate

Abstract: Switches today provide a small menu of scheduling algorithms. While we can tweak scheduling parameters, we cannot modify algorithmic logic, or add a completely new algorithm, after the switch has been designed. This paper presents a design for a programmable packet scheduler, which allows scheduling algorithms-potentially algorithms that are unknown today-to be programmed into a switch without requiring hardware redesign.Our design uses the property that scheduling algorithms make two decisions: in what order … Show more

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Cited by 190 publications
(95 citation statements)
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References 33 publications
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“…While today's switches do not support priority queues, recent work [59,60] has shown that it is feasible to implement programmable priority queues in emerging programmable switching chips [11]. This design allows packets to be inserted into the queue based on a programmable rank value that is computed before the packet is enqueued.…”
Section: The Numfabric Switchmentioning
confidence: 99%
See 1 more Smart Citation
“…While today's switches do not support priority queues, recent work [59,60] has shown that it is feasible to implement programmable priority queues in emerging programmable switching chips [11]. This design allows packets to be inserted into the queue based on a programmable rank value that is computed before the packet is enqueued.…”
Section: The Numfabric Switchmentioning
confidence: 99%
“…This design allows packets to be inserted into the queue based on a programmable rank value that is computed before the packet is enqueued. The paper [60] shows how STFQ can be realized with this design. We omit the details and refer the reader to [60].…”
Section: The Numfabric Switchmentioning
confidence: 99%
“…There are also such as Intel's FlexPipe [6], Cavium's Xpliant [7] and Cisco's Doppler [8] and the other business, using similar programmable pipelines to improve data plane performance. In [9], they proposed a idea of programmable packet scheduler, in the switch to prepare the scheduling algorithm to determine the order of packet scheduling and queue priority.It achieved the programmable hardware, but the increase design cost. In [10] introduced a high-level language programming data plane algorithm, and these programs can be compiled on the emerging switch chip to run at low speed microcode.…”
Section: Research On Programmable Data Planementioning
confidence: 99%
“…These algorithms encompass data-plane traffic engineering, in-network congestion control, active queue management, network security, and measurement. We also used Domino to express the priority computation for programming scheduling using push-in first-out queues [58].…”
Section: Expressivenessmentioning
confidence: 99%
“…These algorithms process and transform packets, reading and writing state in the switch. Examples include active queue management [38,47,51], scheduling [58], congestion control with switch feedback [45,60], network measurement [63,37], and data-plane traffic engineering [21].…”
Section: Introductionmentioning
confidence: 99%