Matching output queueing with a combined input/output-queued switch

Chuang, Shang-Tse; Goel, Ashish; McKeown, Nick; Prabhakar, Balaji

doi:10.1109/49.772430

Cited by 297 publications

(6 citation statements)

References 15 publications

(4 reference statements)

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“…交叉开关由于具有无阻塞特性,实现简单,并且有成熟的商用芯片可直接应用,因而在目前商用路由器交换结构设计中广为应用 [1,2] .然而随着网络技术的发展,路由交换设备必须能够支持更高的端口速率和更密集的端口数量,基于交叉开关构建的交换结构因此面临着越来越多的挑战.输出排队(output queued,简称 OQ)交换结构虽然在提供服务质量(QoS)保障方面极具优势,通过简单的调度机制即可获得高吞吐量和良好的时延性能,然而交换单元和存储单元的 N 倍加速问题使其在高速环境下应用受限 [3] .输入排队(IQ)交换结构虽然无须硬件加速, 并且通过采用虚拟输出排队(virtual output queued,简称 VOQ)机制也可以获得高吞吐量 [4] ,但是其调度过程必须从全局的角度协调交换结构所有输入端口和输出端口的带宽使用,因而算法复杂度较高,在高速环境下不易于硬件实现 [5] .比较而言,联合输入输出排队(CIOQ)交换结构对输出排队机制和输入排队机制进行了较好的折衷,Chuang 等人证明了该交换结构在 2 倍加速时能够完全模拟 OQ 交换结构 [6,7] ,然而 CIOQ 交换结构模拟 OQ 交换结构同样需要集中式的匹配算法,依然具有极高的算法复杂度,因此仅具有理论意义. 一种新的思路是,在交叉开关内部的交叉节点增设小容量的缓存单元,而且近年来随着芯片设计技术的进步和工艺水平的提高,在交叉开关内部实现小容量的节点缓存并不困难 [8] .目前,带缓存交叉开关已经成为交换结构领域新的研究热点,基于带缓存交叉开关构建的联合输入交叉节点排队(CICQ)交换结构因其性能优势更是备受关注 [9] .Magill 等人证明了 CICQ 交换结构在 2 倍加速条件下可以通过分布式调度算法模拟支持 k 个优先级的先入先出输出排队交换结构(first come first served output queued,简称 FCFS-OQ) [10] ;Chuang 等人证明了在 3 倍加速条件下,CICQ 交换结构可以通过分布式调度算法实现模拟采用任意调度算法的 OQ 交换结构 [11] ; 我们证明了当空分复用扩展因子为 2 时,CICQ 交换结构无须加速即可模拟采用任意调度算法的 OQ 交换结构 [12] .CICQ 交换结构模型如图 1 所示,它采用带缓存交叉开关作为核心交换单元,在交换结构的每个输入端口分别设置一个输入缓存单元.为了避免发生队头阻塞,输入缓存单元通常采用虚拟输出排队机制,即每个输入缓存单元在逻辑上被划分为 N 个虚拟输出队列,分别用于缓存到达 N 个输出端口的分组.…”

Section: Cicq交换结构unclassified

Interleaving Coded Multi-Threshold Scheduling Algorithm

Peng¹,

Wang²,

Chen³

et al. 2009

Journal of Software

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An interleaving coded multi-threshold scheduling (ICMTS) algorithm is proposed in this paper. Since the ICMTS algorithm uses the interleaving coded thresholds of two stage queues as the scheduling weights, it can systematically evaluate the scheduling demands of both the input queues and the crosspoint queues. By segmenting the queue length as multiple thresholds, the hardware resource of this algorithm can be largely decreased. It is proved that a CICQ (combined input-crosspoint-queued) switch operating with the ICMTS algorithm can achieve 100% throughput with a speedup of two. To facilitate hardware implementation, a simplified maximal ICMTS scheme is also presented with a time complexity of O(logN). Simulation results show that even the simplified ICMTS scheme can obtain better performance than the existing algorithms.

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Section: Cicq交换结构unclassified

Interleaving Coded Multi-Threshold Scheduling Algorithm

Peng¹,

Wang²,

Chen³

et al. 2009

Journal of Software

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“…Let L be the number of bits arrived at a single input port during a slot time. At the output ports, the OQ buffers (output queues [5]) need to store packets arrived over 2δN S slots. Thus 2δN S L bits are enough for each output port.…”

Section: Buffer Sizementioning

confidence: 99%

“…Assume time on each input/output line is slotted such that each time slot can accommodate a single packet. When the incoming packets arrive, they are first buffered in the VOQs (virtual output queues [5]) at each input port. For every pre-defined T time slots, the buffered packets form an N×N traffic matrix C(T) where N is the switch size.…”

mentioning

confidence: 99%

Two-layer parallel switching: a practical and survivable design for performance guaranteed optical packet switches

Wu¹,

Yeung²,

Li³

2005

GLOBECOM '05. IEEE Global Telecommunications Conference, 2005.

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An optical packet switch (OPS) is called performance guaranteed if it can achieve 100% throughput with bounded packet delay. Presently, high speedup requirement and large packet delay are two main disadvantages in designing performance guaranteed OPS. Survivability is another important issue that must be considered for real OPS implementations. In this paper, we propose a two-layer parallel OPS architecture together with an efficient scheduling scheme to address all the above issues. The tradeoff between speedup and packet delay under this new parallel architecture is also formulated to provide more design flexibility. Compared to the single-layer OPS, our proposed solution can simultaneously reduce both speedup and packet delay. For example, a delay of 4δN slots can be achieved with a speedup of 2 in our solution (where N is the switch size and δ is the switch reconfiguration overhead), whereas the singlelayer OPS needs a speedup of 6 for a delay of 7δN slots. We show that this significant improvement benefits from a careful overall design rather than simply adding an extra switching layer. Keywords-Optical packet switch (OPS); parallel switching; performance guaranteed scheduling; reconfiguration overhead. I. 0-7803-9415-1/05/$20.00 © 2005 IEEE 0-7803-9415-

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“…A moderate speedup of only two together with a stable matching algorithm in a nonblocking crossbar is sufficient to mimic an OQ switch for a large variety of scheduling disciplines [2]. This paper analyses the initial conditions of a stable matching in a CIOQ network switch and to what extent advanced algorithms can improve performance.…”

Section: Introductionmentioning

confidence: 99%

On the performance of advanced stable matching algorithms in combined input output queued network switches

Schweizer

Siliquini

Devadason

2007

2007 Asia-Pacific Conference on Communications

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Combined Input Output Queued switches have emerged as one solution to overcome speedup problems in pure output queued switches. It has been shown that a speedup of two is sufficient to exactly mimic the behavior of an output queued switch when a stable matching algorithm is used. Over the years, a number of advanced stable matching algorithms have been developed and their use is also suggested for network switches. While these algorithms provide considerable improvement for a reference application to which they usually refer, the conditions encountered in a network switch are typically very different.A mathematical analysis and simulation results for a key parameter in stable matchings will be presented. It will be argued that the reduction of iterations with advanced stable matching algorithms in network switches is very limited.

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Matching output queueing with a combined input/output-queued switch

Abstract: -The Internet is facing two problems simultaneously: there is a need for a faster switching/routing infrastructure, and a need to introduce guaranteed qualities of service (QoS

Cited by 297 publications

References 15 publications

Interleaving Coded Multi-Threshold Scheduling Algorithm

Interleaving Coded Multi-Threshold Scheduling Algorithm

Two-layer parallel switching: a practical and survivable design for performance guaranteed optical packet switches

On the performance of advanced stable matching algorithms in combined input output queued network switches

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