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In the pursuit of creating new structures with improved overall mechanical properties, we produced a duplex stainless steel with both high strength and good plasticity, which combines in a harmonized way a refined microduplex structure with a coarse structure. This is accomplished by applying a mixed process of mechanical milling followed by spark-plasma sintering for a duplex steel powder, leading to a microstructure with a gradual and continuous transition between coarse and ultra-fine-grained regions at the microscale. This type of structure is referred to as Harmonic. The grain refinement at the surface of the milled powder particles occurs through the recrystallization of the severely-deformed surface layers during sintering, and results in a microduplex structure which gradually transitions to a coarse duplex structure away from the particles surface. Both the recrystallization mechanism and the effect of this refined structure on the sinterability and final mechanical properties of the compacts are investigated.

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Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.

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