This paper presents a radiation-hardened-by-design (RHBD) phase-locked loop (PLL) which utilizes a feedback voltage controlled oscillator (FBVCO) to mitigate a single event transient (SET) strike. Whenever the SET pulse attacks the input control voltage of VCO, VCO gives rise to a frequency disturbance and PLL produces a huge jitter at the output clock. The proposed FBVCO consists of an open loop VCO, an integrator and a switched-capacitor resistor. The input transfer function of the FBVCO has a low-pass characteristic so that the FBVCO can reduce any perturbation at the input control voltage. In addition, the proposed RHBD PLL reduces size by using one loop filter (LF) and charge pump (CP) compared to prior works. We simulate the proposed scheme in 130 nm low power CMOS technology at 1.5V supply. The output frequency variation of the proposed PLL from the SET strike is 75% smaller than that of previous PLL at 300 MHz. This RHBD PLL consumes 6.2 mW at 400 MHz output frequency.
KeywordsPhase-locked loop (PLL), radiation-hardened-by-design (RHBD), voltage controlled oscillator (VCO), loop filter (LF)
This paper presents a novel phase-locked loop (PLL) architecture to generate a low jitter output clock with a closed loop voltage controlled oscillator (YeO). The proposed closed loop yeO consists of an open loop yeO, an integrator, a non-overlapping clock generator and a switched-capacitor resistor. Because the closed loop yeO has a high-pass characteristic for a yeO noise transfer function and a negative feedback loop suppresses a phase noise of the open loop yeO, the closed loop yeO shows the low phase noise compared to the conventional open loop yeo. Moreover, the closed loop yeO can filter any perturbation at the control voltage due to a low pass characteristic of input voltage transfer function. We design the proposed PLL scheme in 130 nm low power eM OS technology at 1.5Y supply. An integrated RMS j itter is 5.81 psec at 300 MHz output frequency, which is 24% smaller than the jitter of previous PLL with the open loop yeo. The proposed PLL consumes 4.8 mW at 400 MHz output frequency.
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