A low jitter digital phase-locked loop with a hybrid analog/digital PI control

Jung, Seok Min; Roveda, Janet

doi:10.1109/newcas.2015.7182019

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) 2015

DOI: 10.1109/newcas.2015.7182019

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A low jitter digital phase-locked loop with a hybrid analog/digital PI control

Seok Min Jung

Janet Roveda

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2021

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Cited by 2 publications

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A low jitter digital phase-locked loop with a hybrid analog/digital PI control

Cited by 2 publications

References 8 publications

Root Cause Analysis for the Phase Noise of the Clock Generator

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