Design of low jitter phase-locked loop with closed loop voltage controlled oscillator

Abstract

This paper presents a novel phase-locked loop (PLL) architecture to generate a low jitter output clock with a closed loop voltage controlled oscillator (YeO). The proposed closed loop yeO consists of an open loop yeO, an integrator, a non-overlapping clock generator and a switched-capacitor resistor. Because the closed loop yeO has a high-pass characteristic for a yeO noise transfer function and a negative feedback loop suppresses a phase noise of the open loop yeO, the closed loop yeO shows the low phase noise compared to the conventional open loop yeo. Moreover, the closed loop yeO can filter any perturbation at the control voltage due to a low pass characteristic of input voltage transfer function. We design the proposed PLL scheme in 130 nm low power eM OS technology at 1.5Y supply. An integrated RMS j itter is 5.81 psec at 300 MHz output frequency, which is 24% smaller than the jitter of previous PLL with the open loop yeo. The proposed PLL consumes 4.8 mW at 400 MHz output frequency.

Low power design of ultra wideband PLL using 90 nm CMOS technology

“…A PLL system is a closed loop feedback control system that is capable of generating a clock signal that has a fixed relationship to the reference clock signal. The main concept of this system is to match the reference and the feedback signals in phase which is the lock condition by comparing both signals [1]. Figure 1 shows the block diagram of PLL that consists of three sub module blocks namely Phase Frequency Detector (PFD), Charge Pump (CP) and Loop Filter (LF) and Voltage Controlled Oscillator (VCO).…”