By eliminating metal contamination caused by sputtering events occurring behind the wafer as well as in front of the wafer, we have successfully formed ultrashallow, low-reverse-bias-current n+p junctions by postimplantation annealing conducted at a temperature as low as 450~ Further, we propose that the increased leakage current still present in the absence of metallic contamination is due to the residual damage which is the ion-implantation generated point defects widely distributed in the bulk of silicon. Effects of each point defect becomes more pronounced as the annealing temperature is reduced.
Arsenic-implanted self-aligned Al-gate MOSFETs have been successfully fabricated by employing ultra-clean ion implantation technology. The use of ultra high vacuum ion implanter and the suppression of the high-energy-beam-induced metal sputter contamination have enabled us to form low-leakage pn junctions by fumace arurealing at a temperature as low as 450"C. The fabricated Al-gate MOSFETs have exhibited good electrical characteristics, thus demonstratiDg a large poteDtial for application to realizing ultra-high-speed integrated circuits. 1. Introducfion and drain junctions self-aligned to the aluminum gate,
A Si deep-trench etching process using HBr/SF6/O2 plasma was studied. It was found that when the hole trench width was decreased from 190 to 140 nm, erosions at the topmost part of the Si hole sidewall were observed at an incidence of 10 ppm, which was checked from top-down views of 928 million hole shapes per wafer. It was confirmed that when the cathode temperature was increased to 140 °C, no Si erosion occurred. It was found that etching at a higher temperature reduced the halogen content in the film deposited on the sidewall, making the film more protective, and suppressed Si erosion.
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