A promising technique to form the silicon-on-nothing structure is presented as an alternative to the silicon-on-insulator structure. A large plate-shaped empty space in silicon (ESS) below the surface of the silicon substrate can be fabricated by connecting the spherical empty spaces, which are formed by surface migration of Si on the patterned Si substrate. The ESS technique has the potential to change the microprocess for the fabrication of large-scale integrated circuits and it can be applied to various manufacturing technologies.

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The micro-structure transformation of silicon (MSTS), which is a transformation technology for patterning silicon surfaces by hydrogen annealing, is presented for the first time. The transformation was controlled by the parameters of annealing pressure as well as annealing time and temperature. Voids of sub-micrometer regime size can be intentionally formed in the silicon substrates by making use of transformation. Electrical characteristics, such as the reliability of the thin dielectrics formed in the deep trenches, were improved with the aid of the MSTS process, due to the flattening of the inside surface of the trenches and the rounding of the corners. The mechanism of the transformation by MSTS was studied by means of molecular dynamics, which clearly shows the migration of silicon atoms on the surface. MSTS is a promising technology for the fabrication of future integrated circuits in silicon.

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It was found that a high concentration of holes was generated without any post-annealing by boron ion implantation into silicon in the high-dose region of more than 1×1016 cm−2. X-ray photoelectron spectroscopy and Fourier transform infrared absorption spectrum revealed that B12 icosahedra were created just after implantation. The generation of holes can be explained by the model in which B12 icosahedra act as a double acceptor.

We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10nm fin width have been demonstrated.A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall, no spacer on the fin sidewall) is also demonstrated for realizing low-resistance elevated source/drain (S/D) extension. IntroductionFinFETs are promising candidates for sub-20nm scale CMOS devices because of their excellent scalability [1-8]. Primary challenges for FinFETs are the formation of uniform and narrow fins and the reduction of S/D series resistance. The sidewall transfer (SWT) process was proposed to form sub-lithographic fins and reduce the line edge roughness of the fins (Fig.1) [1]. However, the integration technology for the application of SWT process to both fin and gate formation has not been reported yet. On the other hand, it is necessary to deposit silicon selectively on the narrow fins for the reduction of the series resistance by increasing the fin width in S/D regions. However, this process has been very difficult because of the residue of gate sidewall spacer material left on the fin sidewall and the agglomeration of narrow fins.In this paper, we report the FinFET process integration technology including improved SWT process applied to both fins and gates. We also present the device characteristics of the ultra-small FinFET with 15nm gate length and 10nm fin width. A new process technique for the selective gate sidewall spacer formation is also proposed and the advantages of this new approach are experimentally demonstrated.

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