Phase-locked loops (PLLs) are widely used for clock generation in modern digital systems. All-digital PLLs have been proposed to address design issues in conventional analog PLLs. However, current all-digital PLLs require custom circuit design, and therefore cannot fully leverage advanced automated digital design flows. While fully synthesizable PLLs [1,2,3] have been reported, they suffer from high power consumption and large area. This arises because each stage of the ring needs to have a large number of parallel tristate buffers/inverters in order to achieve the necessary frequency resolution. Moreover, custom-designed cells are required in prior synthesizable PLLs [2, 3], introducing additional place-and-route (P&R) steps, leading to poor portability, integration, and scalability. To address these issues, this paper proposes a fully synthesizable PLL based solely on a standard digital library, with a currentoutput digital-to-analog converter (DAC) for maintaining frequency linearity and duty balance, an interpolative phase-coupled oscillator for minimizing the output phase imbalance from automatic P&R, as well as an edge injection technique for avoiding injection-pulse width issues.A block diagram of the proposed PLL with a DAC and an interpolative phasecoupled oscillator is given in Fig. 15.1.1. All circuits that makeup the PLL, including the DAC and DCO, are implemented using standard cells and an automated design flow. A dual-loop PLL architecture [5] is employed and improved in this design to provide continuous tracking of voltage/temperature variations and to avoid the timing problems associated with conventional injection-locked PLLs. The frequencies of two oscillators are digitized by two counters. A signed adder/subtractor compares the digitized frequencies with a predefined frequency-control word (FCW) and provides a frequency difference to a digital loop filter consisting of a proportional path and an integral path. The filter output determines whether to increase, decrease, or hold the DCO oscillation frequency. In addition, an edge-injection technique is incorporated into this design. Figure 15.1.2 illustrates the proposed oscillator architecture that is used in both the main and replica VCOs. In order to relieve the oscillator output phase imbalance caused by the automatic P&R, an interpolative phase-coupled oscillator built by three 3-stage oscillators is developed, based on the concept in [6]. Due to its internal feedback and feed-forward control using phase interpolators for the oscillator, the phase difference within the ring and between all adjacent rings will remain fixed in time, leading to balanced output phases. To maintain the control-code resolution and extend the operating frequency range, the oscillator is designed to operate with a coarse, medium, and fine tuning. A standard cell-based DAC controls the coarse tuning of the oscillator. As shown in Fig. 15.1.2, a digitally-controlled varactor using NAND gates is adopted in the medium-tuning circuitry. The fine-tuning circuitry is real...
