Beamforming (BF) is a smart antenna technique to provide a summation of the weighted signal over multi-users to produce the more concentrated transmitted signal from massive MIMO antenna arrays deployed in a Millimeter-Wave (mm-Wave) 5G heterogeneous wireless network. It adjusts the amplitudes and phases of the signals received over different antennas in an optimum manner in the form of directional radiation. This paper will help in the installation of 5G and 6G mm-Wave heterogeneous wireless networks. Here, adaptive BF is designed and being implemented on the Machine Learning (ML) platform using Signal-to-Noise-Interference Ratio (SINR). The four ML methods having six BF properties to estimate the SINR of Multiple-Input-Multiple-Output (MIMO) - mm-Wave 5G wireless network are explored. The proposed algorithm suppresses noise plus interference and can reduce the power consumption. The python package pyArgus focusing on the BF and direction finding algorithms has been used for 20,000 simulations. The BF features namely noise variance, number of antenna elements, distance between antenna elements, azimuth angular range of receiving array, elevation angular range of receiving array and Direction of Arrival (DOA) of signal i.e. incident angle of Signal-of-Interest (SOI) are used in predicting the SINR. The 10-fold cross-validation experiment is performed to assess the robustness of the best predictive method. By conducting the rigorous simulations, it has been observed that Random Forest (RF) method outperforms over the three other ML methods such as Tree model i.e. rpart, Generalized Linear Model (glm) and Neural Network (nnet), which does the prediction inexpensive and faster. The performance analysis parameters’ result represents that the prediction of Mean Absolute Error (MAE) by RF is lowest 70.73 in value, and its Accuracy is maximum 86.40%, in value having the acceptable error on the training-testing data set.
Millimeter Wave (mm-Wave) - massive Multiple-Input Multiple-Output (MIMO) technology has been a subject of today’s growing interest in both industry and academia for future wireless standards and has significant potential to provide considerable gains in data rates, link reliability and Energy Efficiency (EE).Sparse recovery has great capability in Channel Estimation (CE) for mm-Wave - Massive-MIMO (Ma-MIMO) heterogeneous wireless networks and in this context; the existing better candidate “Orthogonal Matching Pursuit” (OMP) algorithm is modified for CE in such networks. This paper will provide an opportunity in setting up of such a network, and the practical observation of the effect of a change in threshold, sparsity and noise levels as well as quantity of Radio Frequency (RF) chain systems. The performance analysis of CE accuracy in terms of Normalized Mean Square Error (NMSE)verses a given Signal-to-Noise (SNR) range in dB is calculated using this modified algorithm, much better than the existing OMP methods and compared against the ideal Genie case under a wide range of noise encountered. It has been observed that in a very high noise environment, NMSE of this noise resistant algorithm is approximate (100.5 to 10-3.5) in low SNR range (-10 to 30) dB and approximate (10-1.5 to10-5.5) in high SNR range (10 to 50) dB. It comes out to be approximate (10-1 to more than 10-5) in case of combined effect involvingthe reduction of quantity of RF chain systems to half and 10 times enhancement of threshold level in a very high noise environment and low SNR range.
Electronic-dispersion compensation (EDC) techniques are being explored in OC-192 metro and long-haul links to combat dispersion/intersymbol interference (chromatic and polarization mode), noise (optical and electrical), and non-linearities (fiber, photodiode, laser). In this paper, a 9.953 to 12.5Gb/s MLSE receiver, as shown in Fig. 13.2.1, is presented. The receiver is implemented via an AFE IC and a digital equalizer IC that are packaged in a 23×17mm 2 261-pin MCM. The AFE IC is implemented in a 0.18µm 3.3V GHz SiGe BiCMOS process. The digital IC implements the MLSE algorithm and is fabricated in a 0.13µm 1.2V CMOS process.The architecture of the AFE IC is shown in Fig. 13.2.2. It features a VGA, a 4b flash ADC, a dispersion-tolerant clock-recovery unit (CRU), and a 1:8 DEMUX. The ac-coupled line-rate input (9.953 to 12.5Gb/s) can be single-ended or differential. The input signal is amplified by the VGA and then sampled by the ADC. The CRU recovers a line-rate clock for the ADC and the DEMUX. The 4b line-rate ADC samples are demultiplexed 1:8 to generate a 32b LVDS interface to the digital chip (see Fig. 13.2.1).The 3-stage VGA in Fig. 13.2.2 incorporates an analog MUX to achieve a 40dB tunable gain range and an enhanced linearity to meet the requirements of both amplified and un-amplified links. The gain sensitivity to process variations is reduced by employing a replica bias circuit (not shown) to generate source voltage V1 for M1, which is input to the gain-control block, as shown in Fig. 13.2.3. A gain-insensitive offset control maintains a constant offset independent of the input power. Offset control balances the noise variance of '1's and '0's in OSNR-limited links. The need for both single-ended and differential inputs combined with the need for input offset adjustment result in the input-termination scheme in Fig. 13.2.2. A 50Ω input termination is achieved with an S 11 < -15dB up to 7.5GHz and S 11 < -10dB up to 20GHz.The ADC architecture, shown in Fig. 13.2.2, has one stage of preamplifiers followed by two stages of metastability FFs (ADC FFs) and a Gray encoder. The Gray encoder limits coding errors to 1 LSB, minimizing their impact on the BER. The ADC can be configured between a 4b and a power-saving 3b mode. The cascode pre-amp reduces VGA output loading. Isolation between the preamps, the ADC back-end (ADC FFs and the encoder), and the DEMUX is critical. Guard rings are placed between the pre-amps and the ADC back-end, and between the ADC back-end and the DEMUX. The ground and substrate connections of the pre-amps and the ADC FFs are shared to minimize ground bounce. The DEMUX has its own supply, but it shares the same bias current as the ADC FFs. The swing in the digital blocks is made programmable to strike a balance between substrate injection and noise immunity.The CRU shown in Fig. 13.2.2 is a bang-bang PLL [1] with a fast differentially tuned VCO and phase filtering that enables clock extraction in the presence of a closed eye. Fiber non-linearities and dispersion spreads the zero crossings...
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