Managing SRAM reliability from bitcell to library level

Huard, V.; Chevallier, Remy; Parthasarathy, C.; Mishra, Anand; Ruiz-Amador, Natalia; Persin, Flore; Robert, V.; Chimeno, Alejandro; Pion, E.; Planes, N.; Ney, D.; Cacho, F.; Kapoor, Neeraj; Kulshrestha, Vishal; Chopra, Sanjeev; Vialle, Nicolas

doi:10.1109/irps.2010.5488755

Cited by 34 publications

(11 citation statements)

References 4 publications

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“…While the majority of works focus on BTI effects, some recent works have also pointed out the importance of considering the effects of HCI degradation [18], [20], [12]. In fact, authors in [12] have already proposed improving the uniformity of accessess to the cache to mitigate HCI and NBTI degradation.…”

Section: B Experimental Resultsmentioning

confidence: 99%

Resilient random modulo cache memories for probabilistically-analyzable real-time systems

Trilla

Hernández

Abella

et al. 2016

2016 IEEE 22nd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Abstract-Fault tolerance has often been assessed separately in safety-related real-time systems, which may lead to inefficient solutions. Recently, Measurement-Based Probabilistic Timing Analysis (MBPTA) has been proposed to estimate Worst-Case Execution Time (WCET) on high performance hardware. The intrinsic probabilistic nature of MBPTA-commpliant hardware matches perfectly with the random nature of hardware faults. Joint WCET analysis and reliability assessment has been done so far for some MBPTA-compliant designs, but not for the most promising cache design: random modulo. In this paper we perform, for the first time, an assessment of the aging-robustness of random modulo and propose new implementations preserving the key properties of random modulo, a.k.a. low critical path impact, low miss rates and MBPTA compliance, while enhancing reliability in front of aging by achieving a better -yet random -activity distribution across cache sets.

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Section: B Experimental Resultsmentioning

confidence: 99%

Resilient random modulo cache memories for probabilistically-analyzable real-time systems

Trilla

Hernández

Abella

et al. 2016

2016 IEEE 22nd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…As reported in [1], that studies the degradation effects on memories, the logic part is vulnerable to both BTI and HCI, whereas the storage one to BTI only. The degradation mechanisms affect both the performance, in terms of path degradation, and the reliability, in terms of functionality maintainance.…”

Section: Introductionmentioning

confidence: 89%

When processors get old: Evaluation of BTI and HCI effects on performance and reliability

Sandionigi¹,

Héron²,

Bertolini³

et al. 2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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This paper investigates the problem of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) on processors. We propose a performance-and reliability-aware methodology that evaluates the effects of these degradation mechanisms at design time. The performed analysis estimates the effects produced by the execution of applications, representing typical or worst case scenarios, or single instructions. As shown by the experimental results, our framework allows to estimate the performance degradation and to identify the areas of memory most subject to faults, with the objective of optimizing the system design and defining on-line strategies.

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“…While the majority of works focus on BTI effects, some recent works have also pointed out the importance of considering the effects of HCI degradation [16], [18], [10]. In fact, authors in [10] have already proposed improving the uniformity of accesses to the cache to mitigate HCI and NBTI degradation.…”

Section: Related Workmentioning

confidence: 99%

Aging Assessment and Design Enhancement of Randomized Cache Memories

Trilla

Hernández

Abella

et al. 2017

IEEE Trans. Device Mater. Relib.

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Abstract-Critical real-time systems require the estimation of the Worst-Case Execution Time (WCET) for scheduling purposes and resource budgeting. Measurement-Based Probabilistic Timing Analysis (MBPTA) has been shown recently as a powerful approach for WCET estimation. MBPTA builds upon time-randomized cache memories. While aging has been deeply analyzed for conventional time-deterministic caches (i.e. implementing modulo placement), little work has been done to assess the reliability of time-randomized caches. In this line, only the WCET analysis of faulty time-randomized caches has been introduced recently. However, the intrinsic robustness of randomized hardware designs has not been assessed yet. In this paper we perform, for the first time, an assessment of the agingrobustness of random placement cache designs: random modulo and hash-based random placement. We propose a new random modulo implementation preserving its key benefits in terms of low critical path impact, low miss rates and MBPTA compliance; while reducing hot-carrier injection aging by achieving a better -yet random -activity distribution across cache sets. On the other hand we show that gains in terms of BTI aging are limited for random placement designs on their own.

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Managing SRAM reliability from bitcell to library level

Cited by 34 publications

References 4 publications

Resilient random modulo cache memories for probabilistically-analyzable real-time systems

Resilient random modulo cache memories for probabilistically-analyzable real-time systems

When processors get old: Evaluation of BTI and HCI effects on performance and reliability

Aging Assessment and Design Enhancement of Randomized Cache Memories

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