Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter hot carrier injections (HCI). This failure mechanism causes a performance degradation of digital ICs. The evaluation of timing degradations becomes a must-have to ensure the expected timeto-market and IC lifetime early in the design flow. In this paper, we present a design/verification flow at front-end from which we accurately analyze the impact of instruction-set architecture on processor timings. We show results on a RISC processor named AntX and designed in a 40 nm TSMC technology. Using typicalcase scenarios can increase the maximum operating frequency by 15 % on average compared to a worst-case scenario, while considering the same lifetime. We also identify that the shift operations cause the highest timing degradations along the long processor paths.
International audienceDie shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter HCI. This mechanism causes timing degradation and possibly failures in ICs. The evaluation of timing degradation early in the design flow becomes a must-have to ensure the expected time-to-market and IC lifetime. In this paper, we propose a framework for simulating and analyzing the HCI-induced timing variations at high abstraction level. We first present a bottom-up approach to move information about timing degradation up to the higher abstraction layers. Then, we describe a simulation framework for analyzing the HCI-induced timing variations, and we evaluate its performance and accuracy. Finally, by considering a sample processor, we analyze the impact of the instruction set architecture on slack times and critical paths
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