ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) 2014
DOI: 10.1109/esscirc.2014.6942117
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A 8 Gbps blind oversampling CDR with frequency offset compensation over infinite burst

Abhishek Chowdhary
1
,
Alok Kaushik
2
,
S.K. Mandal
3
et al.
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Cited by 4 publications
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A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR

Shekhar
1
,
Inti
2
,
Jaussi
3
et al. 2019
IEEE J. Solid-State Circuits
9
0
4
0
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A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR

Shekhar
1
,
Inti
2
,
Jaussi
3
et al. 2019
IEEE J. Solid-State Circuits
9
0
4
0
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A 2$\times$ Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery

Son
1
,
Ryu
2
,
Yeo
3
et al. 2019
IEEE J. Solid-State Circuits
5
0
0
0
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A Low-Cost 0.00063-mm2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock

Bal
1
,
Singh
2
,
Kumari
3
et al. 2022
IEEE Trans. Circuits Syst. II
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