This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50nm trench pattern, which are lower resistance than Al and good reliabilities.
San #24 Nongseo-Lee, Kihung-Eup, Y ongin-G un, Kyungki-Do, Korea Introduction As the storage electrode area is decreasing with increase of DRAM density, the various stack structures have been extensively developed by a number of researchers. The Fin (1,2), the Spread Stack (3), and the Cylinder families (4,5) are proposed as the possible stack structures for high density DRAM . Recently, HSG (Hemi Spherical Grain ) or Rugged Surface technique (6,7,8) are reported for surface area enhancement.However, the capacitance of those stack structures can hardly satisfy the capacitance requirement for 256Mb DRAM within the limited design rule.This paper introduces MVP ( Micro Yillus Eatterning ) technology which delivers the maximized cell capacitance. With simple process integration, the MVP technology will be a strong candidate for the future stack cell capacitor process.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.