MAPPING DEFECTS within the UltraSparc microprocessor's static RAMs during manufacture serves two purposes, both aimed at yield improvement. One is to locate and map repairable defects. The other is to gain direct insight into process and design issues that lead to defects. Our memory test method emphasizes defect mapping and also allows easy reprogramming of test algorithms-two attributes that set it apart from other approaches.
This paper describes the testability, debuggability, and manufacturubility features of the UltraSPARCTM-I microprocessor. Due to the aggressive nature of this high performance design, these three ureas needed to be adiressed at the beginning of the project to ensure success. We present the goals and analysis that lead to our decisions as well as the actual features that were implemented. The features described in this paper have helped enormously in achieving the time-to-volume goals and hence the overall success of the product.
The 5.2M transistor UItraSPARC(TM)-I microprocessor is manufactured using the 0.5um EPIC3 CMOS QLM process. Design features were implemented to accelerate increases in manufacturing yield and product performance while enabling rapid establishment of high-coverage manufacturing test. Support for production memory defect mapping and repair, scan-based testing and failure analysis, component identity tracking, Iddq testing, per-chip CMOS process parameter monitoring, and aggressive process scalability were included. In implementing these features, our goal was to build a foundation for automatic and continuous identification of bottlenecks in performance of the overall microprocessor manufacturing process.
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