<title>Design of the UltraSPARC-I microprocessor for manufacturing performance</title>

Abstract

The 5.2M transistor UItraSPARC(TM)-I microprocessor is manufactured using the 0.5um EPIC3 CMOS QLM process. Design features were implemented to accelerate increases in manufacturing yield and product performance while enabling rapid establishment of high-coverage manufacturing test. Support for production memory defect mapping and repair, scan-based testing and failure analysis, component identity tracking, Iddq testing, per-chip CMOS process parameter monitoring, and aggressive process scalability were included. In implementing these features, our goal was to build a foundation for automatic and continuous identification of bottlenecks in performance of the overall microprocessor manufacturing process.

Mapping and repairing embedded-memory defects

“…2 Direct, pipelined writes and reads allow capture and mapping of all detected failures. The tester generates defect maps for four memory arrays: a 158-Kbit, single-port instruction cache (containing predecode, instruction cache, and instruction tag blocks); a 128-Kbit, single-port data cache; a 15-Kbit, dual-port data cache tag; and a 16-Kbit, dual-port next-field RAM used for instruction address prediction.…”

Designing UltraSparc for testability

“…This led to requirements set forth by both the manufacturing and design teams for an embedded-memory test mode. 6 These requirements supported s memory defect mapping for yield improvement and laser repair s compatibility with memory testers and logic testers s minimal dependence on processor logic circuits s compatibility with burn-in test equipment s an effective means for failure isolation . s low area impact s operation at full processor speed s the flexibility to apply any memory test algorithm to the arrays under test…”

PADded cache: a new fault-tolerance technique for cache memories

“…Replacement techniques, such as extra rows and columns, are also used in caches for yield enhancement [11] and for tolerating lifetime failures [9] [12]. With replacement techniques, there is no performance loss in caches with faults.…”