Designing UltraSparc for testability

Abstract

ALTHOUGH TESTABILITY is important in designing a high-performance microprocessor, short time to volume-the time it takes to develop, debug, and ramp up production of a design to meet customer demands-is critical. To meet time-to-volume goals for large, complex chips like UltraSparc (see the box), we must optimize test, debug, and manufacture. Thus, the same features that helped UltraSparc meet these goals also helped meet quality goals and reduced debug and product development time. They also provided a means to make incremental improvements in succeeding processor generations. 1

An Efficient Exact Algorithm for Constraint Bipartite Vertex Cover

“…These can be used in an internal (on-chip) or external reconfiguration phase (using lasers to program fuses) where faulty array rows or columns are replaced by spare ones, cf. the recent reports on DEC Alpha and UltraSparc processor manufacturing [7,30,49].…”

“…These ideas are already quite old, see [43] for an early treatment of the topic, but have continued to persist into the most recent developments in VLSI technology. Interestingly, the most challenging (parts of) high-end processors of today are the seemingly simplest of all possible VLSI chips, namely memories due to their rapidly expanding needs; moreover, e.g., they account for approximately 44% of transistors of the UltraSparc processor, so that they are used as technology and yield drivers [30,49]. One common solution to increase yield in memory fabrication is to supply a few spare rows and columns to each memory array.…”

Pentium Pro processor design for test and debug

“…This set of constraints limits Intel microprocessor design teams' ability to use DFT and test generation techniques (full or partial scan and scan-based BIST), which are commonly used in other microprocessors in the industry. [3][4][5][6][7] Within these constraints, the design team optimized the design for low die area, high performance, low power dissipation, high test quality, and low test cost.…”

Symmetric transparent BIST for RAMs

“…Modern computer systems typically contain a variety of embedded memory arrays like caches, branch prediction tables or priority queues for instruction execution [4,14]. Fault free memory operations are crucial for the correct behavior of the complete system, and thus, efficient techniques for production testing as well as for periodic maintenance testing are mandatory to guarantee the required quality standards.…”