&lt;title&gt;Defect mapping and repair in UltraSPARC-I microprocessor memories&lt;/title&gt;

Paramanandam, S.; Youngs, Lynn

doi:10.1117/12.250827

Cited by 1 publication

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“…Since the UltraSPARC arrays can be accessed on an individual cell by cell basis, it is a straight-forward procedure to translate a failure into a physical location. During the manufacturing flow, these fail locations are automatically tracked so that each device can be repaired using spare rows and columns in the array [3]. In terms of failure diagnosis, bitmaps are generated from the fail data to indicate the locartion of likely defects and direct the physical failure analysis [ 5 ] .…”

Section: Defect Mapping and Analysismentioning

confidence: 99%

Diagnostic techniques for the UltraSPARC/sup TM/ microprocessors

Kinra

Mehta²,

Smith³

et al.

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)

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Successful manufacturing ramp of a complex high speed microprocessor requires quick and reliable test and diagnostic methods. Some commonly used debug techniques for the UltraSPARC family of devices are presented with actual result of some diagnosed failures.necessary to develop and automate some key debug flows and procedures.The design-for-test features of the UltraSPARC designs are well defined in [ 1,2,4]. What is not as well documented is the actual usefulness of these features with regard to manufacturing and testing. The results presented in this paper show some of the successes that were achieved because of the strong test methodology in these designs.

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Section: Defect Mapping and Analysismentioning

confidence: 99%