No abstract
This paper describes a Chip Scale Package (CSP) development project and evaluation of the corresponding organic laminate material. Chip scale packaging can combine the strengths of various packaging technologies, such as the large size and performance advantages of a bare die assembly and the reliability of encapsulated devices. Optimizing the laminate carrier material for low CTE reduces the dimensional mis-match between chip and laminate during Bond and Assembly (BA) and mitigates Chip-Package Interactions (CPI) related fails. Utilizing a low CTE material significantly reduces the strain in the solder joints during the reflow process. Modeling laminate CSP groundrules with the organic material parameters provides stress and strain predictions and highlights parameter ranges for successful BA process capability. Predicted global and chip-site warp data from thermo-mechanical modeling are compared to the measured warpage data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated. Electrical and mechanical tests carried out on the low CTE laminate material and subsequently on the related CSP are described. Recommendations for future CSP development and testing are presented.
A low cost ball grid array package has been developed for use with flip chip die. The structural "back bone" of this chip carrier is a metal plate which serves as a built-in heat spreader and a floating ground plane as well as the principal structural member of the package.Thin film circuitry is employed to make the necessary connections between the die and the solder balls. The fine line circuitization enables escape of many I/O from the flip chip die and thus a high VO package with only a single layer of circuitry. The circuit lines are separated fi-om the metal plate by means of a thin polymer dielectric layer. The die is attached to the carrier with a conventional high temperature C4 attach process. The ball grid array is on a 1.27 mm pitch.The metal plate that serves as the structural member of this package provides a number of benefits. The coefficient of thermal expansion (CTE) of the metal plate is very close to the CTE of the circuit card. The size of the package is not limited, therefore, in order to prevent fatigue and fracture of solder balls. The metal plate is separated fi-om the circuitry by only a thin layer of dielectric material. The plate thus serves as a very effective floating ground plane and thereby provides improved electrical performance. The plate also serves as an effective heat spreader, again because of the thin dielectric layer separating the metal plate fiom the circuitry, the die and the solder balls. If added thermal performance is desired, a heat sink is easily attached to the backside of the metal plate.The thin film circuitry employed in this package also provides a number of benefits. The die and the solder balls are connected by a single layer of circuitry. Since electrical vias are not required, low cost processing is possible. Circuitization of the thin film metal can produce extremely fine lines and spaces; more than 700 U 0 can be handled in a single layer.
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