Development of a Low CTE chip scale package

Yamada, Takeshi; Fukui, Masahiro; Terada, Kenji; Harazono, Masaaki; Reynolds, Charles; Audet, Jean; Iruvanti, Sushumna; Liu, Hsichang; Moore, S.; Pan, Yi; Zhang, Hongqing

doi:10.1109/ectc.2013.6575688

Cited by 10 publications

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Much work has been done to mitigate CPI stress and resulting WBs by improving adhesion and fracture toughness of dielectric films [8], improving the via passivation design [5], developing a low CTE organic substrate [9], improving the chip joining process (slow cooling rate post-reflow) [6], developing differential heating/cooling chip joining method [7]. CPI Stresses in the BEOL can be further reduced by using an epoxy compound as an underfill (encapsulation) material for C4s in a flip chip package which helps redistribute and thus mitigate the stress in the C4s.…”

Section: Introductionmentioning

confidence: 99%

Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Pan

Zitz

Questad

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

Self Cite

View full text Add to dashboard Cite

Chip-Package Interaction (CPI) related failure risk has increased in organic laminate-based electronic packages fueled in part by certain industry-segments' requirements for larger silicon die size and signal performance. CPI-related stresses increase directly with radial distance from the center of the die, known as distance from the neutral-point (DNP). The resulting risk of local delamination (White Bumps, WBs) in the silicon back-end-of-line (BEOL), fracture of C4 interconnections and failure of underfill and chip ultimately impact electronic package reliability. Named from the notable visible white halo or circle around a C4 in a CSAM (C-Mode Scanning Acoustic Microscopy) image, WBs are the prime indicator of a CPI-related failure event in an organic laminatebased electronic package.Laminate and BEOL design, specifically wiring proximal to the C4 interconnection, are known to influence WB reliability. In this paper we specifically study the effect of laminate and BEOL design on the generation of white bumps. Four different chip designs, some of which are more susceptible to WBs than others are mated with both productdesign and "flat" laminates, or laminates consisting of only a core and single copper layer on each side. Our ultimate goal is to highlight the silicon & laminate designs' ability to modulate WB occurrences, to create design ground-rules thereby relaxing the cost and facilitating the development of package assembly solutions.A comprehensive experiment was carried out to achieve these goals. As companion test vehicles to product laminates, four different flat laminate (0-2-0) designs were fabricated with several different core materials to both segregate the effect of laminate wiring design and modulate the overall laminate coefficient of thermal expansion (CTE). Four separate chip designs were used to study the effect of the back end of line design.Thermal stress was induced in the experiment using a high-cooling rate or "hammer" chip-join (HCJ) reflow profile which drives a higher C4 shearing stress than with the nominal profile. The occurrence of WBs was then monitored while the test vehicles were repeatedly subjected to the hammer profile in a controlled hammer thermal cycling (HTC) process. Diagnostic measurements including 3D Surface Metrology and CSAM were performed after each HTC cycle to monitor both laminate warpage and WB occurrence respectively. White Bump evolution was statistically analyzed and correlated to each die design, laminate cross-sectional design and CTE. Results demonstrated the importance of laminate design in that the flat laminates consistently lead to fewer WBs than product laminates. Lower-CTE laminates also result in fewer WBs than product laminates. IntroductionChip-package interaction thermo-mechanical stresses (CPI Stress) exist in electronic packages due to the coefficient of thermal expansion mismatch among the different materials used to fabricate the package and critical temperatures (curing) at which these materials are processed. Such stresses can reach th...

show abstract

Section: Introductionmentioning

confidence: 99%

Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Pan

Zitz

Questad

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

Self Cite

View full text Add to dashboard Cite

show abstract

“…These stresses will eventually decrease the reliability of the organic package. Efforts to address the challenges include development of low CTE chip scale package [Yamada et al 2013], design and selection of dielectric materials with compatible properties through thermal-mechanical modeling [Nakanish 2007, Banerji 2002, Iannuzzelli 1991] and fabrication of robust stacked-via structures [Sundaram 2004]. …”

Section: Introductionmentioning

confidence: 99%

Failure mechanism investigation of stacked via cracking in organic chip carrier

Pan

Iruvanti

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

Self Cite

View full text Add to dashboard Cite

The increasing demand for high density interconnects leads to the adoption of stacked via technology. By layering multiple vias directly on top of each other, via stacking allows for more compact and flexible routing. However, due to the geometric discontinuity and non-uniform stiffness, stacked vias also present significant reliability challenges.In the investigation of via stack cracking mechanism in packaging applications, 16 types of stacked and staggered via chain structures were designed and fabricated in an organic chip carrier test vehicle. The experiments were also designed to evaluate other effects such as stacked via location, laminate materials, etc. Comparison of fail counts versus via chain types after 1000 cycles of deep thermal cycling (DTC) revealed that some types of stacked via structures are significantly more robust than others. Strong location dependency of stacked via fail was also observed by comparing the identical stacked via structure in different locations: out of 75 modules, 31 fails were detected in the stacked via chain under the chip center, but none under the chip corner.This paper focuses on the development of a predictive model with finite element method. Modeling activities were carried out to investigate the effect of via structure, package geometry, laminate material and other form factors on via cracking. The thermal-mechanical modeling methodology will be described in this paper. The discussion of failure mechanism and the correlation of simulations with experimental results will be presented. IntroductionOrganic substrates are widely implemented for silicon packaging due to low cost and electrical performance enhancements. The key technology elements of an organic substrate include build-up layers containing most of the wiring, a core and the surface finish for soldering and adhesion. Volume production and low cost of organic substrates were enabled by breakthroughs in laser drilling technology for micro-via, a metalized connecting channel that provides a layer-to-layer connection [Blackshear 2005].The increasing demand for computation performance calls for higher chip frequencies, higher bandwidth, and lower latencies that lead to continuous technology scaling. Moreover, continuous scaling and system integration (adding new and more functionality, such as RF communication, sensors, etc.) require higher I/O density both at the wafer level and at the package level. The 2012 ITRS roadmap calls for organic substrates with lines and spaces below 10um for 16nm technology and beyond [ITRS 2012].

show abstract

Characterization of Copper Diffusion in Through Silicon Vias

Zhang

Lee

2016

Materials for Advanced Packaging

View full text Add to dashboard Cite

Development of a Low CTE chip scale package

Cited by 10 publications

References 4 publications

Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Failure mechanism investigation of stacked via cracking in organic chip carrier

Characterization of Copper Diffusion in Through Silicon Vias

Contact Info

Product

Resources

About