An unconventional application of switched-capacitor (SC) circuits i s discussed in this communication. A systematic method is given for the design of piecewiselinear (PL) arasitic-insensitive SC chaotic discrete maps.A very simpye circuit is re rted which generates a random one-bit digital sequence. &!mulation results show that the random behavior is not significatively altered by large (about 5%) variations in the values of the design parameters, which makes monolithic implementations feasible. Simulation results and layout for a 2pm double metal CMOS prototype are included.
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