Schottky barrier field-effect transistors (SBFETs) based on few and mono layer phosphorene are simulated by the non-equilibrium Green's function formalism. It is shown that scaling down the gate oxide thickness results in pronounced ambipolar I-V characteristics and significant increase of the minimal leakage current. The problem of leakage is especially severe when the gate insulator is thin and the number of layer is large, but can be effectively suppressed by reducing phosphorene to mono or bilayer. Different from two-dimensional graphene and layered dichalcogenide materials, both the ON-current of the phosphorene SBFETs and the metalsemiconductor contact resistance between metal and phosphorene strongly depend on the transport crystalline direction.

Articles you may be interested inEffects of gas environment on electronic and optical properties of amorphous indium zinc tin oxide thin films J. Vac. Sci. Technol. A 31, 031508 (2013); 10.1116/1.4801023 Optical characteristics of pulsed laser deposited Ba0.8Sr0.2TiO3 thin films grown on fused quartz substrate AIP Conf. Highly conductive indium zinc oxide prepared by reactive magnetron cosputtering technique using indium and zinc metallic targets J. Vac. Sci. Technol. A 28, 425 (2010); 10.1116/1.3372806Microstructure investigations of indium tin oxide films cosputtered with zinc oxide at room temperature Transparent conductive indium zinc oxide films were prepared by pulsed plasma deposition from a ceramic target (90 wt. % In 2 O 3 and 10 wt. % ZnO). The dependences of film properties upon the substrate temperature was investigated using characterization methods including x-ray diffraction, atomic force microscope, Hall measurement, ultraviolet-visible spectroscopy, and x-ray photoelectron spectroscopy. The films grown at room temperature had a rather smooth surface due to the amorphous structure, with a root mean square roughness of less than 1 nm. The atomic ratio of Zn/(Zn þ In) in these films is 15.3 at. %, which is close to that in the target, and the chemical states of indium and zinc atoms were In 3þ and Zn 2þ , respectively. The films deposited on a substrate with a temperature of 200 C exhibited polycrystalline structure and a preferred growth orientation along the (222) plane. Here the electrical properties were improved due to the better crystallinity, with the films exhibiting a minimum resistivity value of 4.2 Â 10 À4 X cm, a maximum carrier mobility of 45 cm 2 V À1 s À1 , and an optical transmittance over 80% in the visible region.

Vertical monolayer heterojunction FETs based on transition metal dichalcogenides (TMDCFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent sub-threshold swing, high I ON/IOFF, and high scalability, making them attractive candidates for post-CMOS memory design. This paper explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent device modeling with SRAM circuit design and simulation. Our simulations show that at low operating voltages, TMDCFET and BPFET SRAMs exhibit significant advantages in static power, dynamic read/write noise margin, and read/write delay over both nominal and read/write-assisted 16nm CMOS SRAMs.

Monolayer heterojunction FETs based on vertical heterogeneous transition metal dichalcogenides (TMD-CFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent subthreshold swing, high I ON /I OFF , and high scalability, making them attractive candidates for post-CMOS memory design. This article explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent device modeling with SRAM circuit design and simulation. We perform detailed evaluations of the TMDCFET/BPFET SRAMs at a single bitcell and at SRAM array level. Our simulations show that at low operating voltages, TMDCFET/BPFET SRAMs exhibit significant advantages in static power, dynamic read/write noise margin, and read/write delay over nominal 16nm CMOS SRAMs at both bitcell and array-level implementations. We also analyze the effect of process variations on the performance of TMDCFET/BPFET SRAMs. Our simulations demonstrate that TMDCFET/BPFET SRAMs exhibit high tolerance to process variations, which is desirable for low operating voltages.