Gram negative intracellular pathogen V. parahaemolyticus manifests its infection through a series of effector proteins released into the host via the type III secretion system. Most of these effector proteins alter signalling pathways of the host to facilitate survival and proliferation of bacteria inside host cells. Here, we report V. parahaemolyticus (serotype O3:K6) infection induced histone deacetylation in host intestinal epithelial cells, particularly deacetylation of H3K9, H3K56, H3K18 and H4K16 residues. We found a putative NAD+ dependent deacetylase, vp1524 (vpCobB) of Vibrio parahaemolyticus, was overexpressed during infection. Biochemical assays revealed that Vp1524 is a functional NAD+ dependent Sir2 family deacetylase in vitro, which was capable of deacetylating acetylated histones. Furthermore, we observed that vp1524 is expressed and localized to the nuclear periphery of the host cells during infection. Consequently, Vp1524 translocated to nuclear compartments of transfected cells, deacetylated histones, specifically causing deacetylation of those residues (K56, K16, K18) associated with V. parahaemolyticus infection. This infection induced deacetylation resulted in transcriptional repression of several host genes involved in epigenetic regulation, immune response, autophagy etc. Thus, our study shows that a V. parahaemolyticus lysine deacetylase Vp1524 is secreted inside the host cells during infection, modulating host gene expression through histone deacetylation.

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Vertical monolayer heterojunction FETs based on transition metal dichalcogenides (TMDCFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent sub-threshold swing, high I ON/IOFF, and high scalability, making them attractive candidates for post-CMOS memory design. This paper explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent device modeling with SRAM circuit design and simulation. Our simulations show that at low operating voltages, TMDCFET and BPFET SRAMs exhibit significant advantages in static power, dynamic read/write noise margin, and read/write delay over both nominal and read/write-assisted 16nm CMOS SRAMs.

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Data tampering threatens data integrity in emerging non-volatile memories (NVMs). Whereas Merkle Tree (MT) memory authentication is effective in thwarting data tampering attacks, it drastically increases cell writes and memory accesses, adversely impacting NVM energy, lifetime, and system performance (instructions per cycle (IPC)). We propose ASSURE, a low overhead, high performance Authentication Scheme for SecURE energy efficient (AS-SURE) NVMs. ASSURE synergistically integrates (i) smart message authentication codes (SMACs), which eliminate redundant cell writes by enabling MAC computation of only modified words on memory writes, with (ii) multi-root MTs (MMTs), which reduce MT reads/writes by constructing either high performance static MMTs (SMMTs) or low overhead dynamic MMTs (DMMTs) over frequently accessed memory regions. Our full-system simulations of the SPEC CPU2006 benchmarks on a triple-level cell (TLC) resistive RAM (RRAM) architecture show that on average, SMMT ASSURE (DMMT ASSURE) reduces NVM energy by 59% (55%), increases memory lifetime by 2.36× (2.11×), and improves IPC by 11% (10%), over state-of-the-art MT memory authentication.

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