This paper presents a 3D graphics engine which is specifically designed to minimize the hardware cost while providing sufficient computing capability for consumer electronics with small to medium screen sizes (up to 800x600) such as digital television. The presented 3D engine consists ofa fixedfull 3D graphics pipeline for both geometry and rendering operation. This engine provides a standard AHB interface that makes it easily to be integrated into an AMBA-based SoC. The development of the 3D engine has gone through a rigorous design process. startingfrom system modeling (using System-C), RTL implementation, hardwarelsoftware co-simulation and FPGA verification to test chip fabrication. This 3D engine provides 3.3M verticesls and 2 78Mpixels/s in maximum performance at 139 MHz using 0. 18 silicon technology with 987K gates that is sufficient for most applications for digital television. At the same time, a complete OpenGL-ES 1.] API, windowing system, Linux operating system, device driver and a 3D performance monitoring tool have been developedfor our 3D engine. This performance monitoring tool provides run-time performance information include frame rate, triangle rate, pixel rate, involved OpenGL function list, function counts, memory utilization and etc. Moreover, a built-in real-time AHB bus tracer is also provided to monitor the bus activities of the 3D engine and other components on the system bus. The bus tracer captures on-chip bus signals at ether cycle accurate or transaction levels and applies real-time compression to both levels of signals. With the performance monitoring tool and the bus tracer, the 3D application developer can easily analyze the communication of the components and fine tune the 3D application to optimize the entire SoC system performance and to satisfy performancelcost constrains on consumer electronics. Both of the hardware and software have been carefully verified and demonstrated on FPGA using ARM versatile SoC develop board.
Pre-bond testing of silicon interposer is difficult due to the large number of nets to be tested and small number of test access ports. Recently, it was proposed to include a test interposer that is contacted with the interposer under test in the testing process. Combining these two interposers provides access to nets that are not normally accessible. Previous synthesis method for test interposer was based on constrained breadth-first search, which can be time-consuming. Besides, separate test interposers have to be provided for open and short fault testing. In this paper, we present a theoretical study on the topology of testable circuit structure for interconnect faults in silicon interposer. Based on the theoretical framework, a more efficient synthesis method is developed. Furthermore, a single test interposer can be used for both open and short fault detection, which leads to shorter test time and lower test cost.
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This paper presents a novel scheme for silicon interposer testing. Testing interpose is difficult due to the large number of nets to be tested and small number of test access ports. Thus, previous method can only achieve limited fault coverage for open faults. We propose to include a test interposer that will be contacted with the interposer under test in the testing process. Combining these two interposers will provide access to nets that are not normally accessible; thus, most or all nets become testable. Furthermore, both open and short faults in the interconnect structure can be tested. The efficiency of the proposed test scheme is mainly affected by the structure of test interposer; thus, algorithms for the generation of optimized test interposers are explored. Experimental results show that all faults can be efficiently tested with the proposed method.
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