Fault-tolerant mesh for 3D network on chip

Hsieh, Kai-Yang; Cheng, Bo-Chuan; Gu, Ruei-Ting; Li, Katherine Shu-Min

doi:10.1109/impact.2011.6117292

Cited by 7 publications

(1 citation statement)

References 12 publications

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“…9,10 Additionally, TSV manufacturing processes have high defect rates which result in poor yields. 11,12 Also TSV pads required for bonding consume a considerable amount of area in each layer of the 3D chip. 13 However, most of the work on 3D NoCs in literature assumes full vertical connectivity.…”

Section: Introductionmentioning

confidence: 99%

Heterogeneous 3d Network-on-Chip Architectures: Area and Power Aware Design Techniques

Agyeman

Ahmadinia

Shahrabi

2013

J CIRCUIT SYST COMP

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Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip°oorplan compared to a 2D router. Hence, more e±cient architectures should be designed. In this paper, we propose area e±cient and low power 3D heterogeneous NoC architectures, which combines both the power and performance bene¯ts of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area e±ciency of up to 61% and 19.7%, respectively.

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