Optimized Pre-bond Test Methodology for Silicon Interposer Testing

Abstract

Pre-bond testing of silicon interposer is difficult due to the large number of nets to be tested and small number of test access ports. Recently, it was proposed to include a test interposer that is contacted with the interposer under test in the testing process. Combining these two interposers provides access to nets that are not normally accessible. Previous synthesis method for test interposer was based on constrained breadth-first search, which can be time-consuming. Besides, separate test interposers have to be provided for open and short fault testing. In this paper, we present a theoretical study on the topology of testable circuit structure for interconnect faults in silicon interposer. Based on the theoretical framework, a more efficient synthesis method is developed. Furthermore, a single test interposer can be used for both open and short fault detection, which leads to shorter test time and lower test cost.

Testing of Interposer-Based 2.5D Integrated Circuits

“…However, their silicon interposer only includes interconnects that extend between the opposite major surfaces of the interposer, which differs from the structure of the interposer used in industry. Similar to the conductive glass handler, Li et al proposed the use of a test interposer that is in contact with the interposer under test during the testing process [30,31]. Combining these two interposers provides access to nets that are not normally accessible.…”

“…The testing of thinned wafers is a significant challenge but it can be addressed using techniques that are currently deployed in industry [5,7,31]. Compared to previous methods, e-fuses are less costly and thereby can be used more easily to form test paths.…”