A Low Cost Tile-based 3D Graphics Full Pipeline with Real-time Performance Monitoring Support for OpenGL ES in Consumer Electronics

Abstract

This paper presents a 3D graphics engine which is specifically designed to minimize the hardware cost while providing sufficient computing capability for consumer electronics with small to medium screen sizes (up to 800x600) such as digital television. The presented 3D engine consists ofa fixedfull 3D graphics pipeline for both geometry and rendering operation. This engine provides a standard AHB interface that makes it easily to be integrated into an AMBA-based SoC. The development of the 3D engine has gone through a rigorous design process. startingfrom system modeling (using System-C), RTL implementation, hardwarelsoftware co-simulation and FPGA verification to test chip fabrication. This 3D engine provides 3.3M verticesls and 2 78Mpixels/s in maximum performance at 139 MHz using 0. 18 silicon technology with 987K gates that is sufficient for most applications for digital television. At the same time, a complete OpenGL-ES 1.] API, windowing system, Linux operating system, device driver and a 3D performance monitoring tool have been developedfor our 3D engine. This performance monitoring tool provides run-time performance information include frame rate, triangle rate, pixel rate, involved OpenGL function list, function counts, memory utilization and etc. Moreover, a built-in real-time AHB bus tracer is also provided to monitor the bus activities of the 3D engine and other components on the system bus. The bus tracer captures on-chip bus signals at ether cycle accurate or transaction levels and applies real-time compression to both levels of signals. With the performance monitoring tool and the bus tracer, the 3D application developer can easily analyze the communication of the components and fine tune the 3D application to optimize the entire SoC system performance and to satisfy performancelcost constrains on consumer electronics. Both of the hardware and software have been carefully verified and demonstrated on FPGA using ARM versatile SoC develop board.

A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization

“…In Comparison, because reverse encoding has a good compression rate, the traced cycle is 4.86x of the industrial case. As for the periodical triggering, (Assuming the best case of 8 segments) We have integrated the on-chip bus tracer within a 3D graphics SoC platform [10] as shown in Fig. 12.…”

The development of an energy-awared mobile 3D graphics SoC with real-time performance/energy monitoring and control

“…Compared to state-ofart DLL, we can achieve 20% faster lock time. Besides, due to all digital circuits in the proposed DLL, it can also reduce 10 to 20% power consumption compared to those of counterparts; (2) Power Measurement System (current measurement circuits, analog-to-digital converter, and automatic calibration): We propose a unique on-chip power measurement system for the real-time power management. It can provide sufficient power consumption information for power management to analysis and can adjust the voltage and/or frequency of related building blocks; (3) Development of low-power cell circuits and interfaces between different clock domains and different voltage domains: The design of low voltage cell can be used for other projects which can utilize the advantage of low power design.…”

“…Since 2005, we have cooperated with Himax Inc. to build a low cost tile-based 3DG SoC, called SYS-3DG Core I, which consists of a 3DG engine and an embedded debugging/ performance monitoring engine (EDPME) [2]- [4]. Recently, the obvious driving force behind low-power and low-energy with high performance systems comes from the SoC d e v e l o p m e n t o f p o r t a b l e m o b i l e c o m p u t i n g a n d communication.…”