An efficient HW/SW integrated verification methodology for 3D Graphics SoC development

Ho, Tsung-Yu; Chen, Liang-Bi; Huang, Ing-Jer

doi:10.1109/isce.2009.5157044

2009 IEEE 13th International Symposium on Consumer Electronics 2009

DOI: 10.1109/isce.2009.5157044

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An efficient HW/SW integrated verification methodology for 3D Graphics SoC development

Tsung-Yu Ho

Liang-Bi Chen

Ing-Jer Huang

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2009

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An efficient HW/SW integrated verification methodology for 3D Graphics SoC development

Cited by 1 publication

References 8 publications

A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement

A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement

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