No abstract

A widely tunable 4th order BPF based on the subtraction of two 2nd order 4-path passive-mixer filters with slightly different center frequencies is proposed. The center frequency of each 4-path filter is slightly shifted relative to its clock frequency (one upward and the other one downward) by a gm-C technique. Capacitive splitting of the input signal is used to reduce the mutual loading of the two 4-path BPFs and increase their quality factors. The filter is tunable from 0.4 GHz to 1.2 GHz with approximately constant bandwidth of 21 MHz. The in-band 1-dB compression point of the filter is −4.4 dBm while the in-band IIP3 of the filter is +9 dBm and the out of band IIP3 is +29 dBm (∆f= +50 MHz). The ultimate rejection of the filter is >55 dB and the NF of the filter is 10 dB. The static and dynamic current consumption of the filter are 2.8 mA from 2.5 V and 12 mA from 1.2 V, respectively (at 1 GHz). The LO leakage power to the input port is <−60 dBm. The filter has been fabricated in CMOS LP 65 nm technology and the active area is 0.127 mm 2 .

No abstract

Integrated class-D audio amplifiers are very power efficient but require an external LC reconstruction filter, which prevents further integration. Also due to this filter, large feedback factors are hard to realize, so that the load influences the distortion and transfer characteristics. The 30-W amplifier presented in this paper consists of a switching part that contains a much simpler filter and a linear part that ensures a low distortion and flat frequency response. The switching part of the amplifier was integrated in a BCD process. Combined with a linear part and with a loudspeaker as load, it has a flat frequency response 6 6 60.3 dB, a dissipation that is up to five times lower than a traditional class-AB audio amplifier, and a distortion of < < <0.02% over power and frequency range.

The analysis and design of a highly-efficient 80V class-D power stage design in a 0.14µm SOIbased BCD process is described. It features immunity to the on-chip supply bounce, realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and low switching loss are achieved with 94% peak efficiency for the complete class-D power stage in the realized chip.

Co-existence problems in a mobile terminal environment pose strict requirements on the linearity of a front-end receiver. In this paper, active feedback is explored as a means to relax such requirements by providing channel selectivity as early as possible in the receiver chain. The proposed receiver architecture addresses some of the most common problems of integrated RF filters, while maintaining their inherent tunability. Through a simplified and intuitive analysis, the operation of the receiver is examined and the design parameters affecting the filter characteristics, such as bandwidth and stop-band rejection, are determined. A systematic procedure for analyzing the linearity of the receiver reveals the possibility of LNA distortion canceling, which decouples the trade-off between noise, linearity and harmonic radiation.A prototype designed in a standard 65nm CMOS process occupies < 0.06mm 2 and utilizes an RF channel-select filter with a 1-to-2.5GHz tunable center frequency to achieve 48dB of stop-band rejection and a wideband IIP3 > +12dBm.

No abstract

This paper describes the power dissipation analysis and the design of an efficiency-improved high-voltage class-D power amplifier. The amplifier adaptively regulates its switching frequency for optimal power efficiency across the full output power range. This is based on detecting the switching output node voltage level at the turn-on transition of the power switches. Implemented in a 0.14µm SOI BCD process, the amplifier achieves 93% efficiency at 45W output power, >80% power efficiency down to 4.5W output power and >49% efficiency down to 0.45W output power.