2015
DOI: 10.1109/jssc.2015.2421994
|View full text |Cite
|
Sign up to set email alerts
|

A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range

Abstract: This paper describes the power dissipation analysis and the design of an efficiency-improved high-voltage class-D power amplifier. The amplifier adaptively regulates its switching frequency for optimal power efficiency across the full output power range. This is based on detecting the switching output node voltage level at the turn-on transition of the power switches. Implemented in a 0.14µm SOI BCD process, the amplifier achieves 93% efficiency at 45W output power, >80% power efficiency down to 4.5W output po… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
21
0

Year Published

2016
2016
2022
2022

Publication Types

Select...
5
2

Relationship

0
7

Authors

Journals

citations
Cited by 22 publications
(21 citation statements)
references
References 24 publications
(42 reference statements)
0
21
0
Order By: Relevance
“…The level shifter and the gate driver of each output transistor are powered by a floating regulator that provides a 5V local supply with respect to the source of each output transistor. M2, M3, M5, and M7 require local supplies above PVDD, which are obtained using external bootstrap capacitors CBSTP and CBSTN charged respectively through internal Schottky diodes DBSTP and DBSTN, as in [2,[21][22][23]. M2 and M5 (also M3 and M7) employ separate regulators to avoid crosstalk-induced timing errors due to voltage droop at the regulator outputs during gate charging.…”
Section: A Architecturementioning
confidence: 99%
See 1 more Smart Citation
“…The level shifter and the gate driver of each output transistor are powered by a floating regulator that provides a 5V local supply with respect to the source of each output transistor. M2, M3, M5, and M7 require local supplies above PVDD, which are obtained using external bootstrap capacitors CBSTP and CBSTN charged respectively through internal Schottky diodes DBSTP and DBSTN, as in [2,[21][22][23]. M2 and M5 (also M3 and M7) employ separate regulators to avoid crosstalk-induced timing errors due to voltage droop at the regulator outputs during gate charging.…”
Section: A Architecturementioning
confidence: 99%
“…8 shows the gate driver design, which buffers the level shifter output and drives the output transistors. To reduce loading on the floating regulator, most of the gate charge is drawn from the floating regulator's input directly using a source follower MN1 [2,23]. In the last stage, the pull-down strength is chosen to be larger than the pull-up strength to avoid cross conduction and to allow minimal dead time, which reduces the output stage distortion [22].…”
Section: E Gate Drivermentioning
confidence: 99%
“…Several factors contribute to the overall power dissipation in the output power stage [19], [23], the dominant ones include Fig. 5.…”
Section: Output Power Stagementioning
confidence: 99%
“…Generally, the DC-DC converter control consists of one output variable as it uses one or two control variables [26], [27], [28], [29]. More specifically, the DC-DC converter employs a voltage control in which the output voltage is controlled by being detecting it and using the pulse width or the frequency as a control variable; alternatively, the output voltage is controlled by detecting it and the inductor current and using the duty cycle or the frequency as a control variable [30].…”
Section: High Efficiency Tracking Controller Designmentioning
confidence: 99%