A High-Linearity and Low-EMI Multilevel Class-D Amplifier

Abstract

This paper presents a Class-D audio amplifier for automotive applications. Low EMI and, hence, smaller LC filter size is obtained by employing a fully differential multilevel output stage switching at 4.2 MHz. A modulation scheme with minimal switching activity at zero input reduces idle power, which is further assisted by a gate-charge reuse scheme. It also achieves high linearity thanks to the high loop gain realized by a 3 rd -order feedback loop with a bandwidth of 800 kHz. The prototype, fabricated in a 180 nm high-voltage BCD process, achieves a minimum THD+N of −107.8 dB/−102 dB and a peak efficiency of 91%/87% with an 8-Ω and a 4-Ω load, respectively, while drawing 7 mA quiescent current from a 14.4 V supply. The prototype meets the CISPR 25 Class 5 EMI standard with a 5.7 dB margin using an LC filter with a cutoff frequency of 580 kHz.

A Chopper Class-D Amplifier for PSRR Improvement Over the Entire Audio Band

“…A fully differential 3 rd order loop filter based on active RC integrators is employed (Fig. 2) for high loop gain [13,25], with 𝑓𝑓 𝑈𝑈 = 570 kHz. The 1 st stage of A 1 is chopped to boost its CMRR and eliminate its 1/f noise.…”

“…In a 200-run Monte Carlo simulation, chopping improves the worst-case CMRR of A 1 from 87 dB to 108 dB. The OTAs in the loop filter are designed in a two-stage feedforward compensated topology for high GBW, which helps to suppress IM at the virtual ground of the 1 st integrator OTA due to chopping, as mentioned in Section III-C. To perform PWM, a differential triangle wave produced by an RC oscillator is compared with the loop filter output [25]. The input chopper employs conventional bootstrapping for high linearity.…”

A -109.1 dB/-98 dB THD/THD+N Chopper Class-D Amplifier with >83.7 dB PSRR Over the Entire Audio Band

“…Back-to-back LDMOS transistors are used to block the conduction path through the body diodes when the switches are turned off. The chopper clocks are transferred from the LV digital domain (1.8 V) to the HV domain by level shifters [7], each powered by a local regulator. All regulators are sourced by a charge pump that provides a ~28 V supply.…”

“…CCP is charged by Cbst1 and Cbst2 in an alternating fashion in each PWM cycle, holding VCP up to ~28 V. The level shifter is shown in Fig. 5a [7]. Depending on the PWM signal and the chopping phase, VREG1,2,3,4 are either ~5 V or ~19.4 V. This introduces a signal-dependent delay in the level shifter since, in the former case, the bias current source M1 operates in the triode region for part of the transition.…”

“…A PWM modulator driven by an on-chip oscillator runs at 2.1 MHz, which allows a relatively high loop gain for high linearity. A 3 rd order loop filter [5,7] is employed, which provides >80 dB loop gain within the audio band to suppress the distortion of the output power stage. The input stage of the 1 st integrator's OTA is sized such that its 1/f noise corner frequency is below fCHOP.…”