A Chopper Class-D Amplifier for PSRR Improvement Over the Entire Audio Band

Abstract

The power supply rejection ratio (PSRR) of conventional differential closed-loop Class-D amplifiers is limited by the feedback and input resistor mismatch and finite CMRR of the OTA in the 1 st integrator. This paper presents a 14.4 V Class-D amplifier employing chopping to tackle the mismatch, thereby improving the PSRR. However, chopping-induced intermodulation within a PWM-based class-D amplifier can severely degrade PSRR and linearity. Techniques to mitigate such intermodulation are proposed and analyzed. To chop the 14.4V PWM output signal, a high-voltage (HV) chopper employing DMOS transistors is developed. Its timing is carefully aligned with that of the low-voltage (LV) choppers to avoid further linearity degradation. The prototype, fabricated in a 180 nm BCD process, achieves a PSRR of >110 dB at low frequencies, which remains above 79 dB up to 20 kHz. It achieves a THD of −109.1 dB and can deliver a maximum of 14 W into an 8-Ω load with 93% efficiency while occupying a silicon area of 5 mm 2 . Index Terms-Audio power amplifier, class-D amplifier, intermodulation, power supply rejection ratio (PSRR), total harmonic distortion (THD).C Fig. 1. Conventional closed-loop Class-D amplifier in a BTL configuration and sources of limited PSRR: feedback resistor mismatch, input resistor mismatch, and finite CMRR of the OTA in the 1 st integrator.

A 121.4-dB DR Capacitively Coupled Chopper Class-D Audio Amplifier

“…This is because the value of R dc would have to be much larger to push the preamplifier's high-pass corner below 20 Hz, instead of below f CH in the case of chopping. Furthermore, chopping relaxes the matching constraint on C FB and C IN pairs, thereby improving the common-mode rejection of the preamp and, therefore, power supply rejection ratio (PSRR) of the CDA [26].…”

“…Chopping is performed at f CH = 200 kHz, an odd subharmonic of f SW , to avoid the chopping-induced intermodulation distortion (IMD) [27] due to PWM sidebands around f SW [26]. A lower chopping frequency would require a lower 1/ f corner for A 1 , increasing its input capacitance, and thus its area and power, whereas a higher chopping frequency increases IMD due to PWM sidebands around even multiples of f SW and the deadband's noise folding gain.…”

“…11. Schematic of the floating regulator and level shifter [26]. A replica of this circuit is used for timing skew correction.…”

“…The input chopper (CH IN ) is implemented with conventional bootstrapped switches for high linearity. The feedback chopper (CH FB ) is also bootstrapped and employs back-to-back LDMOS switches to handle the output up to 14.4 V [26], as shown in Fig. 10.…”

“…12(a) and (b). A replica-based timing skew correction circuit is employed to reduce the timing skew from more than 3 ns to be within 200 ps [26].…”