This paper presents a continuous-time (CT) zoom ADC for use in audio applications. Compared to previous zoom ADCs, its input impedance is mainly resistive, making it much easier to drive while still maintaining high energy efficiency. The prototype is fabricated in a 0.16 pm CMOS process, occupies 0.27 mm2 and achieves 108.5 dB DR, 108.1 dB SNR, 106.4 dB SNDR in a 20 kHz BW, while consuming 618 pW. This results in a state-of-the-art Schreier FoM of 183.6 dB.
This paper presents a Class-D audio amplifier for automotive applications. Low EMI and, hence, smaller LC filter size is obtained by employing a fully differential multilevel output stage switching at 4.2 MHz. A modulation scheme with minimal switching activity at zero input reduces idle power, which is further assisted by a gate-charge reuse scheme. It also achieves high linearity thanks to the high loop gain realized by a 3 rd -order feedback loop with a bandwidth of 800 kHz. The prototype, fabricated in a 180 nm high-voltage BCD process, achieves a minimum THD+N of −107.8 dB/−102 dB and a peak efficiency of 91%/87% with an 8-Ω and a 4-Ω load, respectively, while drawing 7 mA quiescent current from a 14.4 V supply. The prototype meets the CISPR 25 Class 5 EMI standard with a 5.7 dB margin using an LC filter with a cutoff frequency of 580 kHz.
This paper presents a 28W Class-D amplifier for automotive applications. The combination of a high switching frequency and a hybrid multi-bit ∆ΣM-PWM scheme results in high linearity over a wide range of output power, as well as low AM-band EMI. As a result, only a small (150kHz cutoff frequency), and thus low-cost, LC filter is needed to meet the CISPR-25 EMI average limit (150kHz-30MHz) with 10dB margin. At 28W output power, the proposed amplifier achieves 91% efficiency while driving a 4Ω load from a 14.4V supply. It attains a peak THD+N of 0.00077% (-102.2dB) for a 1kHz input signal.
This paper presents a continuous-time zoom ADC for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuoustime delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160 nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1 dB peak SNR, 106.4 dB peak SNDR and 108.5 dB dynamic range in a 20 kHz bandwidth, while consuming 618 μW. This results in a Schreier FoM of 183.6 dB. Index Terms-A/D conversion, audio ADC, delta-sigma ADC, asynchronous SAR ADC, inverter-based OTA, low power circuits, dynamic zoom ADC, continuous-time delta-sigma.
This article describes a discrete-time zoom analogto-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta-sigma modulator (M) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC's quantization noise into the audio band. The prototype ADC occupies 0.27 mm 2 in a 0.16-μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW. It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB. Index Terms-A/D conversion, asynchronous SAR analogto-digital converter (ADC), audio ADC, delta-sigma ADC, discrete-time (DT) delta-sigma, dynamic zoom ADC, inverter-based operational transconductance amplifier (OTA), low-power circuits, multi-bit quantizer. I. INTRODUCTION A UDIO applications often require analog-to-digital converters (ADCs) with high dynamic range (DR), high energy efficiency, and low area [1]-[3]. By combining a lowpower successive-approximation register (SAR) ADC with a high-resolution delta-sigma modulator (M), zoom ADCs can meet all these requirements [4], [5]. The SAR ADC determines the coarse references of the fine M, drastically reducing loop filter swing and enabling energy-efficient design. The overall digital output is then obtained by simply summing the outputs of both converters. Recently proposed Ms with finite impulse response (FIR) DACs and negative-R-assisted integrators are also capable of satisfying the requirements of audio applications [2], [3], [6], [7]. An FIR DAC essentially filters out the fed back quantization noise and, thereby, also relaxes
This article describes a discrete-time zoom analogto-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta-sigma modulator (M) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC's quantization noise into the audio band. The prototype ADC occupies 0.27 mm 2 in a 0.16-μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW. It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB. Index Terms-A/D conversion, asynchronous SAR analogto-digital converter (ADC), audio ADC, delta-sigma ADC, discrete-time (DT) delta-sigma, dynamic zoom ADC, inverter-based operational transconductance amplifier (OTA), low-power circuits, multi-bit quantizer. I. INTRODUCTIONA UDIO applications often require analog-to-digital converters (ADCs) with high dynamic range (DR), high energy efficiency, and low area [1]-[3]. By combining a lowpower successive-approximation register (SAR) ADC with a high-resolution delta-sigma modulator (M), zoom ADCs can meet all these requirements [4], [5]. The SAR ADC determines the coarse references of the fine M, drastically reducing loop filter swing and enabling energy-efficient design. The overall digital output is then obtained by simply summing the outputs of both converters.Recently proposed Ms with finite impulse response (FIR) DACs and negative-R-assisted integrators are also capable of satisfying the requirements of audio applications [2], [3], [6], [7]. An FIR DAC essentially filters out the fed back quantization noise and, thereby, also relaxes
This paper presents a dynamic zoom analog-todigital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16-μm CMOS process, the prototype occupies 0.26 mm 2 and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 μW. This results in a Schreier figure of merit (FoM) of 185.8 dB. Index Terms-A/D conversion, asynchronous successive approximation register analog-to-digital converter, batterypowered applications, delta-sigma ADC, dynamic zoom ADC, inverter-based operational transconductance amplifier (OTA), low-power circuits. I. INTRODUCTIONS LOWLY changing signals, with bandwidths below 1-2 kHz, are often encountered in several applications, such as sensor interfaces, biomedical signal processing, and industrial instrumentation. The amplitude of such signals may vary considerably, ranging from a few microvolts to a few volts, and so analog-to-digital converters (ADCs) are intended for such applications that require wide dynamic range (DR) (>above 120 dB, i.e., 20-bit resolution) and high linearity. Since many of these applications involve battery-powered systems, such as wearable medical devices and portable instruments, such ADCs should also be extremely energy efficient with a power consumption less than a milliwatt. Linearity requirements in such applications also necessitate an integral non-linearity (INL) within a few parts-per-million (ppm), translating into a signal-to-noise-and-distortion-ratio (SNDR) similar to the DR.Successive approximation register (SAR) ADCs are well known for their excellent energy efficiency but their resolution is typically limited to about 12 bits unless extensive calibration
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