This paper presents a continuous-time (CT) zoom ADC for use in audio applications. Compared to previous zoom ADCs, its input impedance is mainly resistive, making it much easier to drive while still maintaining high energy efficiency. The prototype is fabricated in a 0.16 pm CMOS process, occupies 0.27 mm2 and achieves 108.5 dB DR, 108.1 dB SNR, 106.4 dB SNDR in a 20 kHz BW, while consuming 618 pW. This results in a state-of-the-art Schreier FoM of 183.6 dB.
This paper presents a Class-D audio amplifier for automotive applications. Low EMI and, hence, smaller LC filter size is obtained by employing a fully differential multilevel output stage switching at 4.2 MHz. A modulation scheme with minimal switching activity at zero input reduces idle power, which is further assisted by a gate-charge reuse scheme. It also achieves high linearity thanks to the high loop gain realized by a 3 rd -order feedback loop with a bandwidth of 800 kHz. The prototype, fabricated in a 180 nm high-voltage BCD process, achieves a minimum THD+N of −107.8 dB/−102 dB and a peak efficiency of 91%/87% with an 8-Ω and a 4-Ω load, respectively, while drawing 7 mA quiescent current from a 14.4 V supply. The prototype meets the CISPR 25 Class 5 EMI standard with a 5.7 dB margin using an LC filter with a cutoff frequency of 580 kHz.
This paper presents a 28W Class-D amplifier for automotive applications. The combination of a high switching frequency and a hybrid multi-bit ∆ΣM-PWM scheme results in high linearity over a wide range of output power, as well as low AM-band EMI. As a result, only a small (150kHz cutoff frequency), and thus low-cost, LC filter is needed to meet the CISPR-25 EMI average limit (150kHz-30MHz) with 10dB margin. At 28W output power, the proposed amplifier achieves 91% efficiency while driving a 4Ω load from a 14.4V supply. It attains a peak THD+N of 0.00077% (-102.2dB) for a 1kHz input signal.
This paper presents a continuous-time zoom ADC for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuoustime delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160 nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1 dB peak SNR, 106.4 dB peak SNDR and 108.5 dB dynamic range in a 20 kHz bandwidth, while consuming 618 μW. This results in a Schreier FoM of 183.6 dB. Index Terms-A/D conversion, audio ADC, delta-sigma ADC, asynchronous SAR ADC, inverter-based OTA, low power circuits, dynamic zoom ADC, continuous-time delta-sigma.
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