This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1=f noise and hence the oscillator's close-in phase noise. More specifically, it is shown that the 1=f 3 phase noise is dependent on the gate-source voltage of the MOS transistors in the off state. Measurement results, corrected for waveform-dependent upconversion and effective bias, show an 8-dB-lower 1=f 3 phase noise than expected. It will be shown that this can be attributed to the intrinsic 1=f noise reduction effect due to periodic on-off switching.

Integrated class-D audio amplifiers are very power efficient but require an external LC reconstruction filter, which prevents further integration. Also due to this filter, large feedback factors are hard to realize, so that the load influences the distortion and transfer characteristics. The 30-W amplifier presented in this paper consists of a switching part that contains a much simpler filter and a linear part that ensures a low distortion and flat frequency response. The switching part of the amplifier was integrated in a BCD process. Combined with a linear part and with a loudspeaker as load, it has a flat frequency response 6 6 60.3 dB, a dissipation that is up to five times lower than a traditional class-AB audio amplifier, and a distortion of < < <0.02% over power and frequency range.

A relaxation oscillator design is described, which has a phase noise rivaling ring oscillators, while also featuring linear frequency tuning. We show that the comparator in a relaxation-oscillator loop can be prevented from contributing to 1/f 2 colored phase noise and degrading control linearity. The resulting oscillator is implemented in a power efficient way with a switched-capacitor circuit. The design results from a thorough analysis of the fundamental phase noise contributions. Simple expressions modeling the theoretical phase noise performance limit are presented, as well as a design strategy to approach this limit. To verify theoretical predictions, a relaxation oscillator is implemented in a baseline 65 nm CMOS process, occupying 200 mm  150 mm. Its frequency tuning range is 1-12 MHz, and its phase noise is L(100kHz) = À109dBc/Hz at f osc = 12MHz, while consuming 90 mW. A figure of merit of À161dBc/Hz is achieved, which is only 4 dB from the theoretical limit.

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