PECVD silicon nitride photonic wire waveguides have been fabricated in a CMOS pilot line. Both clad and unclad single mode wire waveguides were measured at ¼ 532, 780, and 900 nm, respectively. The dependence of loss on wire width, wavelength, and cladding is discussed in detail. Cladded multimode and singlemode waveguides show a loss well below 1 dB/cm in the 532-900 nm wavelength range. For singlemode unclad waveguides, losses G 1 dB/cm were achieved at ¼ 900 nm, whereas losses were measured in the range of 1-3 dB/cm for ¼ 780 and 532 nm, respectively.
Mode-locked lasers find their use in a large number of applications, for instance, in spectroscopic sensing, distance measurements, and optical communication. To enable widespread use of mode-locked lasers, their on-chip integration is desired. In recent years, there have been multiple demonstrations of monolithic III-V and heterogeneous III-V-on-silicon mode-locked lasers. However, the pulse energy, noise performance, and stability of these mode-locked lasers are limited by the relatively high linear and nonlinear waveguide loss, and the high temperature sensitivity of said platforms. Here, we demonstrate a heterogeneous III-V-on-silicon-nitride (III-V-on-SiN) electrically pumped mode-locked laser. SiN’s low waveguide loss, negligible two-photon absorption at telecom wavelengths, and small thermo-optic coefficient enable low-noise mode-locked lasers with high pulse energies and excellent temperature stability. Our mode-locked laser emits at a wavelength of 1.6 μm, has a pulse repetition rate of 3 GHz, a high on-chip pulse energy of ≈2 pJ, a narrow RF linewidth of 400 Hz, and an optical linewidth <1 MHz. The SiN photonic circuits are fabricated on 200 mm silicon wafers in a CMOS pilot line and include an amorphous silicon waveguide layer for efficient coupling from the SiN to the III-V waveguide. The III-V integration is done by micro-transfer-printing, a technique that enables the transfer of thin-film devices in a massively parallel manner on a wafer scale.
We present a chip-based optical beam scanner based on a dispersive optical phased array (OPA) that illuminates the far field with a pixelated pattern. To scale up the OPA to a large number of antennas, we break it up into manageable blocks with acceptable losses. The 2D wavelength scanning within a block is handled by dispersive delay lines. Between blocks, there are no delay lines, and the OPA will only have constructive interference for a discrete set of wavelengths. This results in the far-field illumination of a pixelated pattern along both x and y directions. The sidelobes and the power in the main lobe can be controlled by the power distribution of the individual OPA antennas.
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