The design of networks for massively parallel computers is strongly influenced b y available technology. The latency, critical for many applications, is signijicantly increased b y packaging constraints, a. e . many connections between switches involve pad drivers or even line drivers. This paper concentrates on reducing those influences f o r a butterfly network related to Ranade 's routing algorithm [I 71. We are implementing such a network f o r a PRAM with 128 physical processors and l28K logical processors. The required throughput makes it critical to use shared busses and improves the problem of space. Whale delays caused by switches can only be hidden b y mapping many virtual processors to some physical ones, connection latency may be reduced by additional registers (shorter clock cycle tame) and suitable mapping schemes (less space). Suitable clustering of processor modules and network parts may additionally decrease the network delay.
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