On the Physical Design of PRAMs

Abolhassan, Ferri; Drefenstedt, Reinhard; Keller, Jörg; Paul, Wolfgang J.; Scheerer, Dieter

doi:10.1007/978-3-322-95233-2_1

Cited by 33 publications

(8 citation statements)

References 4 publications

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“…If both input bu ers of a routing switch contain packets, the one with the smaller hashed address proceeds. If both addresses are identical, the two packets are combined into one 1 . The sorted order guarantees that all packets destined for the same address will meet and be combined into one.…”

Section: Fluent Machine Principlesmentioning

confidence: 99%

On the Physical Design of PRAMs

Abolhassan¹

1993

The Computer Journal

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The Saarbr ucken Parallel Random Access Machine (SB-PRAM) is a scalable shared memory machine. At the gate level it is a re-engineered version of the Fluent machine A. G. Ranade, S. N. Bhatt and S. L. Johnson. The Fluent Abstract Machine. In Proc. 5th MIT Conference on Advanced Research in VLSI, pp. 71{93 (1988)]. It uses hashing of adresses, combining and latency hiding. A prototype with 128 processors is presently being designed. In this paper we deal with several problems related to the physical design of this machine such as the total number of network chips, the geometrical arrangement of boards in the network and the VLSI realization of certain sorting arrays. We also present an extremely fast method to rehash addresses without use of external memory.

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Section: Fluent Machine Principlesmentioning

confidence: 99%

On the Physical Design of PRAMs

Abolhassan¹

1993

The Computer Journal

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“…The SB-PRAM which is currently under construction at the University of Saarbriicken is an UMA machine that provides a shared address space with a fast memory access time [1]. The latency of the network between the processors and the memory modules is hidden by pipelining of processors, i.e., each physical processor simulates a number of virtual processors.…”

Section: Execution Platformmentioning

confidence: 99%

“…The runtime of the reimplementation can be split into four phases: 1. Simulation of logical processes, 2. buffer tests, generation of messages and handling of SIMO, LNE and global activation lists, 3.…”

Section: Performancementioning

confidence: 99%

Scalability Analysis for Conservative Simulationof Logical Circuits

1999

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We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend the critical path analysis technique by partitioning strategies. To incorporate overhead due to the management of data structures, we use a simulation on an ideal parallel machine (PRAM). This simulation can be directly executed on the SB-PRAM prototype, yielding both an implementation and a basis for data structure optimizations. One of the major tools to achieve these optimizations is the SB-PRAM's hardware support for parallel prefix operations. Our reimplementation of the PTHOR program on the SB-PRAM yields substantially higher speedups than before.

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“…The pram model provides a convenient abstraction that combines the simplicity of the ram model with the power of parallelism -this makes the pram easy to "program" using a high-level notation. There is ongoing research [1,28] developing hardware platforms that can be used to efficiently execute algorithms expressed in pram-like programming languages. However, pram makes assumptions that, given the current state of technology, make it difficult for it to be implemented as a scalable parallel architecture.…”

Section: Introductionmentioning

confidence: 99%

Failure-Sensitive Analysis of Parallel Algorithms With Controlled Memory Access Concurrency

Georgiou

Russell

Shvartsman

2007

Parallel Process. Lett.

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The abstract problem of using P failure-prone processors to cooperatively update all locations of an N-element shared array is called Write-All. Solutions to Write-All can be used iteratively to construct efficient simulations of PRAM algorithms on failure-prone PRAMS. Such use of Write-All in simulations is abstracted in terms of the iterative Write-All problem. The efficiency of the algorithmic solutions for Write-All and iterative Write-All is measured in terms of work complexity where all processing steps taken by the processors are counted. This paper considers determinitic solutions for the Write-All and iterative Write-All problems in the fail-stop synchronous CRCW PRAM model where memory access concurrency needs to be controlled. A deterministic algorithm of Kanellakis, Michailidis, and Shvartsman [16] efficiently solves the Write-All problem in this model, while controlling read and write memory access concurrency. However it was not shown how the number of processor failures f affects the work efficiency of the algorithm. The results herein give a new analysis of the algorithm [16] that obtain failure-sensitive work bounds, while retaining the known memory access concurrency bounds. Specifically, the new result expresses the work bound as a function of N, Pandf. Another contribution in this paper is the new failure-sensitive analysis for iterative Write-All with controlled memory access concurrency. This result yields tighter bounds on work (vs. [16]) for simulations of PRAM algorithms on fail-stop PRAMS.

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On the Physical Design of PRAMs

Cited by 33 publications

References 4 publications

On the Physical Design of PRAMs

On the Physical Design of PRAMs

Scalability Analysis for Conservative Simulationof Logical Circuits

Failure-Sensitive Analysis of Parallel Algorithms With Controlled Memory Access Concurrency

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