On the Physical Design of PRAMs

Abolhassan, Ferri

doi:10.1093/comjnl/36.8.756

Cited by 45 publications

(16 citation statements)

References 5 publications

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“…Furthermore, ROMM routing is suitable for store{and{forward, virtual cut{through, and wormhole routed networks, unlike 1 For example, dimension{order routing performs poorly when routing transpose permutations on 2{dimensional meshes. Figure 1: High{level architecture of a network interface for a generic processor node in an n{dimensional network.…”

Section: Related Workmentioning

confidence: 99%

“…Let R = (R0; R1; : : : ; Rn 1 ) be the routing set for a message originating at node X = (x0; x1; : : : ; xn 1 The cardinality jRj of a routing set is de ned as the number of dimensions for which jRij 6 = 0, 0 i < n. The most well{known deterministic, oblivious routing algorithm is dimension{order routing (DimOrder). In DimOrder routing messages are moved from source to destination by correcting the displacements in ascending dimension order 3 .…”

Section: Preliminariesmentioning

confidence: 99%

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ROMM routing on mesh and torus networks

Nesson

Johnsson

1995

Proceedings of the Seventh Annual ACM Symposium on Parallel Algorithms and Architectures - SPAA '95

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ROMM is a class of Randomized, Oblivious, Multi{phase, Minimal routing algorithms. ROMM routing o ers a potential for improved performance compared to both fully randomized algorithms and deterministic oblivious algorithms, under both light and heavy loads. ROMM routing also offers close to best case performance for many common routing problems. In previous work, these claims were supported by extensive simulations on binary cube networks 30, 31]. Here we present analytical and empirical results for ROMM routing on wormhole routed mesh and torus networks. Our simulations show that ROMM algorithms can perform several representative routing tasks 1.5 to 3 times faster than fully randomized algorithms, for medium{sized networks. Furthermore, ROMM algorithms are always competitive with deterministic, oblivious routing, and in some cases, up to 2 times faster.1 Introduction E cient data motion has been critical in high performance computing as long as computers have been in existence. Massively parallel computers use a sparse interconnection network between processing nodes with local memories. Minimizing the potential for high congestion of communication links is an important goal in the design of routing algorithms and networks. Moreover, the packaging technology introduces constraints on the data motion bandwidth at module boundaries, such as chips and boards.These constraints suggest that preserving locality of reference with careful data allocation and minimizing network load by using minimal algorithms are desirable objectives. However, it is important to note that minimal algorithms and locality preserving data mappings do not always guarantee the best routing times. In fact, for certain problems, non{minimal routing algorithms and data allocations which do not preserve locality can utilize more of the available network bandwidth and cause less communication link congestion, without the corresponding increase in demand for network bandwidth.In this paper, we report on a class of minimal algorithms designed to keep the risk of severe congestion low

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Section: Related Workmentioning

confidence: 99%

Section: Preliminariesmentioning

confidence: 99%

ROMM routing on mesh and torus networks

Nesson

Johnsson

1995

Proceedings of the Seventh Annual ACM Symposium on Parallel Algorithms and Architectures - SPAA '95

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“…At programming language level this makes possible to use shared variables and eliminates the need for lockings and atomic operations unless the program declares asynchronous tasks at high level in purpose [21] [22]. Past attempts to realize a PRAM include the omega network-based NYU Ultracomputer [31], CEDAR [16] and IBM Research Parallel Processor Prototype (RP3) [28], butterfly-based Fluent machine [29], 3D torus-based Cray MTA supercomputer [2] and its successors MTA2 and XMT provided by Cray, multiport memory-based solution [4], and butterfly-based SB-PRAM [1,22]. Unfortunately, these attempts have been mainly unsuccessful due to sub-optimal solutions, like non-scalable interconnect topologies, inefficient co-exploitation of multiple levels parallelism, sub-optimal shared memory emulation algorithms, and out-dated prototyping technologies.…”

Section: Introductionmentioning

confidence: 99%

A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads

Forsell¹

2011

IJNC

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It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy parallel programmability crucial to wider penetration of CMPs to general purpose computing. This implementation relies on exploitation of the slack of parallel applications to hide the latency of the memory system instead of caches, sufficient bisection bandwidth to guarantee high throughput, and hashing to avoid hot spots in intercommunication. Unfortunately this solution can not handle workloads with low thread-level parallelism (TLP) efficiently because then there is not enough parallel slackness available for hiding the latency. In this paper we show that integrating non-uniform memory access (NUMA) support to the PRAM implementation architecture can solve this problem and provide a natural way for migration of the legacy code written for a sequential or multi-core NUMA machine. The obtained PRAM-NUMA hybrid model is defined and architectural implementation of it is outlined on our ECLIPSE ESM CMP framework. A high-level programming language example is given.

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“…1 MP3D is not present in the SPLASH 2 benchmark suite [16] Various combinations of address hashing, combining and multithreading are used in machines like the NYU ultracomputer [8,11], the Fluent Machine [12], Cray T3D [1], TERA [5] and the SB-PRAM [2].…”

Section: Introduction and Previous Workmentioning

confidence: 99%

Performance of MP3D on the SB-PRAM Prototype

Dementiev

Klein

Paul

2002

Euro-Par 2002 Parallel Processing

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Abstract. The SB-PRAM is a shared memory machine which hides latency by simple interleaved context switching and which can be expected to behave almost exactly like a PRAM if all threads can be kept busy. We report measured run times of various versions of the MP3D benchmark on the completed hardware of a 64 processor SB-PRAM. The main findings of these experiments are: 1) parallel efficiency is 79% for 32 processors and 56% for 64 processors. 2) Parallel efficiency is limited by the number of available threads. 3) Run time overhead in the SB-PRAM network and in the memory modules due to congestion is less that 1%.

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On the Physical Design of PRAMs

Cited by 45 publications

References 5 publications

ROMM routing on mesh and torus networks

ROMM routing on mesh and torus networks

A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads

Performance of MP3D on the SB-PRAM Prototype

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