Scalability Analysis for Conservative Simulationof Logical Circuits

Abstract

We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend the critical path analysis technique by partitioning strategies. To incorporate overhead due to the management of data structures, we use a simulation on an ideal parallel machine (PRAM). This simulation can be directly executed on the SB-PRAM prototype, yielding both an implementation and a basis for data structure optimizations. One of the major tools to achieve these optimizations is the SB-PRAM's hardware support for parallel prefix operations. Our reimplementation of the PTHOR program on the SB-PRAM yields substantially higher speedups than before.

A Tutorial on Advanced Dynamic Monte Carlo Methods for Systems With Discrete State Spaces

“…Discrete-event simulations are used in an extremely wide range of applications in science, technology, manufacturing, and sociology. Just a few recent examples include preventative veterinary medicine [98], resource allocation following a terrorist bombing [99], modeling concrete supply and delivery [100], aircraft design [101], ecological models [102,103], design of logical circuits [104,105], manufacturing systems [106], battlefield simulations [107], and simulation of wireless services [108]. For the Ising model the method of paral-lelization is to place a block of spins, say ℓ×ℓ in two dimensions, on a processing element.…”