On the physical design of butterfly networks for PRAMs

Drefenstedt, Reinhard; Schmidt, Dirk

doi:10.1109/fmpc.1992.234958

Cited by 4 publications

(1 citation statement)

References 10 publications

(3 reference statements)

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“…Hardware approaches for executing high-contention crcw steps without hot spots incorporate combining logic into the interconnection network. Ranade's work [57] shows that any crcw step can be simulated on certain hypercube-based networks in the same asymptotic time as an erew step, and development of machines based on his technique have been reported (e.g., [1,18]). It is an open question whether the system cost of supporting crcw efficiently in hardware is justified, particularly on mimd machines, and work continues in this area (e.g., [16]).…”

Section: Crcw May Be Too Powerfulmentioning

confidence: 99%

The Queue-Read Queue-Write PRAM Model: Accounting for Contention in Parallel Algorithms

Gibbons¹,

Matias²,

Ramachandran³

1998

SIAM J. Comput.

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Abstract. This paper introduces the queue-read queue-write (qrqw) parallel random access machine (pram) model, which permits concurrent reading and writing to shared-memory locations, but at a cost proportional to the number of readers/writers to any one memory location in a given step. Prior to this work there were no formal complexity models that accounted for the contention to memory locations, despite its large impact on the performance of parallel programs. The qrqw pram model reflects the contention properties of most commercially available parallel machines more accurately than either the well-studied crcw pram or erew pram models: the crcw model does not adequately penalize algorithms with high contention to shared-memory locations, while the erew model is too strict in its insistence on zero contention at each step.The qrqw pram is strictly more powerful than the erew pram. This paper shows a separation of log n between the two models, and presents faster and more efficient qrqw algorithms for several basic problems, such as linear compaction, leader election, and processor allocation. Furthermore, we present a work-preserving emulation of the qrqw pram with only logarithmic slowdown on Valiant's bsp model, and hence on hypercube-type noncombining networks, even when latency, synchronization, and memory granularity overheads are taken into account. This matches the bestknown emulation result for the erew pram, and considerably improves upon the best-known efficient emulation for the crcw pram on such networks. Finally, the paper presents several lower bound results for this model, including lower bounds on the time required for broadcasting and for leader election.Key words. models of parallel computation, parallel algorithms, pram, memory contention, work-time framework AMS subject classifications. 68Q05, 68Q22, 68Q25PII. S009753979427491 1. Introduction. The parallel random access machine (pram) model of computation is the most-widely used model for the design and analysis of parallel algorithms (see, e.g., [40,39,58]). The pram model consists of a number of processors operating in lock-step and communicating by reading and writing locations in a shared memory. Existing pram models can be distinguished by their rules regarding contention for shared memory locations. These rules are generally classified into two groups:• Exclusive read/write: Each location can be read or written by at most one processor in each unit-time pram step.• Concurrent read/write: Each location can be read or written by any number of processors in each unit-time pram step. For concurrent writing, the value written depends on the write-conflict rule of the model, e.g., in the arbitrary concurrent-write pram, an arbitrary processor succeeds in writing its value.

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Section: Crcw May Be Too Powerfulmentioning

confidence: 99%