Reduction of network cost and wiring in Ranade's butterfly routing

Cross, David; Drefenstedt, Reinhard; Keller, Jörg

doi:10.1016/0020-0190(93)90217-w

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Cited by 5 publications

(1 citation statement)

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“…As shown in Figure 4, parts of different nodes are integrated into one chip. This reduces the wiring effort off-chip [7]. Each ASIC represents two complete nodes of the network.…”

Section: Networkmentioning

confidence: 99%

Building the 4 processor SB-PRAM prototype

Bach

Braun

Formella

et al.

Proceedings of the Thirtieth Hawaii International Conference on System Sciences

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“…As shown in Figure 4, parts of different nodes are integrated into one chip. This reduces the wiring effort off-chip [7]. Each ASIC represents two complete nodes of the network.…”

Section: Networkmentioning

confidence: 99%

Building the 4 processor SB-PRAM prototype

Bach

Braun

Formella

et al.

Proceedings of the Thirtieth Hawaii International Conference on System Sciences

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Real PRAM Programming

Paul

Bach

Bosch

et al. 2002

Euro-Par 2002 Parallel Processing

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A note on implementing combining networks

Keller

Walle

1995

Information Processing Letters

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In shared-memory multiprocessors, combining networks serve to eliminate hot spots due to concurrent access to the same memory location. Examples are the NYU Ultracomputer, the IBM RP3 and the Fluent Machine. We present a problem that occurs when one tries to implement the Fluent M a c hine's network nodes with network chips that do not know their position within the network. We f o r m ulate the problem mathematically and present t wo solutions. The rst solution requires some additional hardware around nodes that can be put outside network chips. The second solution requires a minor modi cation of the routing algorithm, but one can prove that there is no performance loss.

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Reduction of network cost and wiring in Ranade's butterfly routing

Cited by 5 publications

References 7 publications

Building the 4 processor SB-PRAM prototype

Building the 4 processor SB-PRAM prototype

Real PRAM Programming

A note on implementing combining networks

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