Real PRAM Programming

Paul, Wolfgang J.; Bach, Peter M.; Bosch, Michael; Fischer, Jörg; Lichtenau, Cedric; Röhrig, Jochen

doi:10.1007/3-540-45706-2_71

Cited by 8 publications

(11 citation statements)

References 11 publications

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“…Since the model assumes that global memory accesses are not more expensive than local ones, which is far from reality, its speedup prediction is typically inconsistent with the speedups observed on real parallel machines. This limitation has been addressed by tailor-made hardware [632,806] and a number of extensions (cf. [23,533] and the references therein).…”

Section: Prammentioning

confidence: 99%

Chapter 5. Realistic Computer Models

Ajwani¹,

Meyerhenke²

2010

Algorithm Engineering

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Section: Prammentioning

confidence: 99%

Chapter 5. Realistic Computer Models

Ajwani¹,

Meyerhenke²

2010

Algorithm Engineering

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“…Earlier attempts to support PRAM by a multi-chip multiprocessor (e.g. TERA-MTA [2], SB-PRAM [17], NYU Ultracomputer and the IBM RP3, [1,10]) have been constrained on memory access performance and had limited success.…”

Section: Impact On Single-chip Parallel Processingmentioning

confidence: 99%

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

Balkan¹,

Horak²,

Qu³

et al. 2007

15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007)

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Section: Impact On Single-chip Parallel Processingmentioning

confidence: 99%

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

Dukkipati

Gibb

McKeown³

et al. 2007

15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007)

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A Mesh of Trees (MoT) on-chip interconnection network has been proposed recently to provide high throughput between memory units and processors for single-chip parallel processing [5]. In this paper, we report our findings in bringing this concept to silicon. Specifically, we conduct cycle-accurate verilog simulations to verify the analytical results claimed in [5]. We synthesize and obtain the layout of the MoT interconnection networks of various sizes. To further improve throughput, we investigate different arbitration primitives to handle load and store, the two most common memory operations. We also study the use of pipeline registers in large networks when there are long wires. Simulation based on full network layout demonstrates that significant throughput improvement can be achieved over the original proposed MoT interconnection network. The importance of this work lies in its validation of performance features of the MoT interconnection network, as they were previously shown to be competitive with traditional network solutions. The MoT network is currently used in an eXplicit Multi-Threading (XMT) on-chip parallel processor, which is engineered to support parallel programming. In that context, a 32-terminal MoT network could support up to 512 on-chip XMT processors. Our 8-terminal network that could serve 8 processor clusters (or 128 total processors), was also accepted recently for fabrication.

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Real PRAM Programming

Cited by 8 publications

References 11 publications

Chapter 5. Realistic Computer Models

Chapter 5. Realistic Computer Models

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

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