Building the 4 processor SB-PRAM prototype

Bach, Peter M.; Braun, Michael; Formella, Arno; Friedrich, J.; Grün, Thomas; Lichtenau, Cedric

doi:10.1109/hicss.1997.663155

Cited by 11 publications

(10 citation statements)

References 34 publications

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“…Multi-chip multi-processor designs such as the NYU-Ultracomputer [11], CRAY/Tera MTA [1] and the SB-PRAM [2,9] are representative examples. Although XMT shares some features with these 3 architectures, XMT is different from them as it is a single chip architecture.…”

Section: Related Workmentioning

confidence: 99%

Fpga-based prototype of a pram-on-chip processor

Wen

Vishkin

2008

Proceedings of the 5th Conference on Computing Frontiers

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PRAM (Parallel Random Access Model) has been widely regarded a desirable parallel machine model for many years, but it is also believed to be "impossible in reality." As the new billion-transistor processor era begins, the eXplicit Multi-Threading (XMT) PRAM-On-Chip project is attempting to design an on-chip parallel processor that efficiently supports PRAM algorithms. This paper presents the first prototype of the XMT architecture that incorporates 64 simple in-order processors operating at 75MHz. The microarchitecture of the prototype is described and the performance is studied with respect to some micro-benchmarks. Using cycle accurate emulation, the projected performance of an 800MHz XMT ASIC processor is compared with AMD Opteron 2.6GHz, which uses similar area as would a 64-processor ASIC version of the XMT prototype. The results suggest that an only 800MHz XMT ASIC system outperforms AMD Opteron 2.6GHz, with speedups ranging between 1.57 and 8.56.

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Section: Related Workmentioning

confidence: 99%

Fpga-based prototype of a pram-on-chip processor

Wen

Vishkin

2008

Proceedings of the 5th Conference on Computing Frontiers

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“…In general, the global memory space is partitioned over the modules, and accesses to different modules are handled concurrently. A universal hashing type approach can be used to avoid pathological access patterns [1,3,10]. Figure 1 depicts a Uniform Memory Access (UMA) type memory structure used in a recent single-chip parallel architecture, which is designed to optimize single-task completion time [14].…”

Section: A Memory Architecture For Single-chip Parallelismmentioning

confidence: 99%

An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing

Balkan

Vishkin

2008

Proceedings of the 45th Annual Design Automation Conference

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Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and low latency at relatively high area cost.In this paper, we introduce a hybrid MoT-BF network that combines MoT network with the area efficient butterfly network. We prove that the hybrid network reduces MoT network's area cost. Cycle-accurate simulation and post-layout results all show that significant area reduction can be achieved with negligible performance degradation, when operating at same clock rate.

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“…This basic memory architecture and incorporation of hashing to avoid hot spots were discussed in [8][9][10][11] For background, it is also important to understand the demand on the interconnection network in the XMT single-chip parallelism context. The messages between processor cluster and the cache modules are very small (e.g., one word for load instructions and at most two words for the store instructions).…”

Section: The Basic Xmt Organizationmentioning

confidence: 99%

“…Although interesting, multi-chip multiprocessor designs that aim to support the PRAM (such as Tera/Cray MTA [8] and SB-PRAM [9]) are constrained by inter-chip interconnections. Latency and bandwidth problems have limited their success in supporting PRAM.…”

Section: Introductionmentioning

confidence: 99%

Plasmonics and the parallel programming problem

2007

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While many parallel computers have been built, it has generally been too difficult to program them. Now, all computers are effectively becoming parallel machines. Biannual doubling in the number of cores on a single chip, or faster, over the coming decade is planned by most computer vendors. Thus, the parallel programming problem is becoming more critical. The only known solution to the parallel programming problem in the theory of computer science is through a parallel algorithmic theory called PRAM. Unfortunately, some of the PRAM theory assumptions regarding the bandwidth between processors and memories did not properly reflect a parallel computer that could be built in previous decades. Reaching memories, or other processors in a multi-processor organization, required off-chip connections through pins on the boundary of each electric chip. Using the number of transistors that is becoming available on chip, on-chip architectures that adequately support the PRAM are becoming possible. However, the bandwidth of off-chip connections remains insufficient and the latency remains too high. This creates a bottleneck at the boundary of the chip for a PRAM-On-Chip architecture. This also prevents scalability to larger "supercomputing" organizations spanning across many processing chips that can handle massive amounts of data. Instead of connections through pins and wires, power-efficient CMOS-compatible on-chip conversion to plasmonic nanowaveguides is introduced for improved latency and bandwidth. Proper incorporation of our ideas offer exciting avenues to resolving the parallel programming problem, and an alternative way for building faster, more useable and much more compact supercomputers.

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Building the 4 processor SB-PRAM prototype

Abstract: The SB-PRAM is a massively parallel, uniform memory access (UMA)

Cited by 11 publications

References 34 publications

Fpga-based prototype of a pram-on-chip processor

Fpga-based prototype of a pram-on-chip processor

An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing

Plasmonics and the parallel programming problem

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