Abstract

SRAM stability during word line disturb (access disturb) is becoming a key constraint for V,, scaling 111. Figure 1 illustrates the access disturb mechanism. In this paper we present a design methodology for $RAM stability during access disturb. In this methodology, the SRAM Access Disturb Margin (ADM) is defined as the ratio of the magnitude of the critical current to maintain SRAM stability ( I c~m ) to the sigma of ICKIT. Using ADM as a figure of merit, this methodology enables one to project the cell stability margin due to process variations, e.g. V, variation, during design of a SRAM cell. Using statistical analysis, the required stability margin for an application requirement such as array size and available redundancy can be estimated. Direct cell probing and m a y test can be used to verify that the stability target is met. SRAM Stability Margin Parameter Static [voltage] noise margin, as measured by the opening in the butterfly curve (Fig. 2) has often been used as a metric for SRAM stability [2]. Two drawbacks of the static noise margin are the inability to measure it with automatic inline testers and the inability to generate statistical information on SRAM fails. Alternatively, the SRAM "N-curve" [3] provides a way to satisfy both needs. Inline parametric testem can measure the voltage and the current on one intemal node of the same test structure used for the butterfly curve.Measured and simulated N-curves with both the word line and bit line held at VDU are shown in Figures 3 and 4. In Fig. 4, intercept I is determined by the SRAM pull down to transfer ritio (SRAM p ratio), while intercept 2 is related to the pull down to pull up relative strength (inverter p ratio). With the bit line held at VOO , if intercept I crosses intercept 2 when the word line tums on, the SRAM cell flips; mrtking the cell unstable during word line disturb. The delta between intercept 1 and 2 can thus be interpreted as thc static noise margin, or the critical voltage to maintain the SRAM stability (VCRIT). One can also characterize the cell stability by the peak current (IcRm). or the total area of the "barrier height" between intercept I and 2 in the unit of power (P,-R,T). As seen in Fig. 4, all three measures of stability are degraded when process variation is included in the simulation. We have confirmed by a Monte Carlo simulation that bits that fail due to VT variation have margin parameters equal to zero. Note that in Fig. 6 , I C~T has a relatively linear relationship with VT'S. To enable linear analysis and extrapolation, we chose ICm as the margin parameter. SRAM Design for Stability MethodologyTo obtain the stability margin, we start with the canonical form:in which x, can be any parameter whose variation is of interest. In this work we focus on the VT variation as the first order effect (x,=V,,). We find that no specific VT correlation between transistors in an SRAM cell best describes the data, but one should note that some correlation could be expected depending on the cell layout details. The total...

We report that the ion implantation of a small dose of Mo into a silicon substrate before the deposition of a thin film of Ti lowers the temperature required to form the commercially important low resistivity C54 -TiSi 2 phase by 100-150°C. A lesser improvement is obtained with W implantation. In addition, a sharp reduction in the dependence of C54 formation on the geometrical size of the silicided structure is observed. The enhancement in C54 formation observed with the ion implantation of Mo is not explained by ion mixing of the Ti/Si interface or implant-induced damage. Rather, it is attributed to an enhanced nucleation of C54 -TiSi 2 out of the precursor high resistance C49-TiSi 2 phase.

We demonstrate that the temperature at which the C49 TiSi2 phase transforms to the C54 TiSi2 phase can be lowered more than 100 °C by alloying Ti with small amounts of Mo, Ta, or Nb. Titanium alloy blanket films, containing from 1 to 20 at. % Mo, Ta, or Nb were deposited onto undoped polycrystalline Si substrates. The temperature at which the C49–C54 transformation occurs during annealing at constant ramp rate was determined by in situ sheet resistance and x-ray diffraction measurements. Tantalum and niobium additions reduce the transformation temperature without causing a large increase in resistivity of the resulting C54 TiSi2 phase, while Mo additions lead to a large increase in resistivity. Titanium tantalum alloys were also used to form C54 TiSi2 on isolated regions of arsenic doped Si(100) and polycrystalline Si having linewidths ranging from 0.13 to 0.56 μm. The C54 phase transformation temperature was lowered by over 100 °C for both the blanket and fine line samples. As the concentration of Mo, Ta, or Nb in the Ti alloys increase, or as the linewidth decreases, an additional diffraction peak appears in in situ x-ray diffraction which is consistent with increasing amounts of the higher resistivity C40 silicide phase.

As the minimum VLSI feature size continues to scaie down to the 0.1-0.2-ju.m regime, the need for iow-resistance iocai interconnections wiii become increasingiy critical. Although reduction in the MOSFET channel length will remain the dominant factor in achieving higher circuit performance, existing local interconnection materials will impose greater than acceptable performance limitations. We review the state-of-the-art salicide and polycide processes, with emphasis on work at IBM, and discuss the limitations that pertain to future implementations in high-performance VLSI circuit applications. A brief review of various silicide-based and tungsten-based approaches for forming local interconnections is presented, along with a more detailed description of a tungsten-based "damascene" local interconnection approach.

No abstract

We have used in situ resistance versus temperature measurements to demonstrate that a 60 nm titanium thin film on polycrystalline silicon heated at rates up to 3000 °C/min always forms high-resistivity base-centered orthorhombic C49-TiSi2 before the low-resistivity face-centered orthorhombic C54-TiSi2 phase. Kinetic analysis of the shift in transformation temperatures with heating rate indicates that the activation energies for the formation of C49-TiSi2 and C54-TiSi2 are 2.1±0.2 and 3.8±0.5 eV, respectively, when formed during the same annealing cycle. The higher activation energy of formation of C54-TiSi2 as compared to C49-TiSi2 suggests that under very high heating rates and annealing temperatures, the formation of C49-TiSi2 before C54-TiSi2 might be completely or partially bypassed.

Lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices. The threshold voltage of both NMOSFETs and PMOSFETs increases in magnitude for conventional retrograde wells, but for triple-well isolated NMOSFETs the threshold voltage decreases for narrow devices near the edge of the well. Electrical data, SIMS, and SUPREM4 simulations are shown that elucidate the phenomenon.