Fluctuation limits &amp; amp; scaling opportunities for CMOS SRAM cells

Bhavnagarwala, A.J.; Kosonocky, Stephen; Radens, C.; Stawiasz, K.; Mann, R. W.; Ye, Qiuyi; Chin, Ken K.

doi:10.1109/iedm.2005.1609437

Cited by 141 publications

(90 citation statements)

References 12 publications

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“…If V write is larger than V trip of {T 3,T 5} inverter, the write will fail. Since T 2 and T 6 (also T 1 and T 5) are typically the smallest transistors in the cell, V th variations in these transistors causes large variation in V write , resulting in a high probability of write failure [6].…”

Section: Soft Error Tolerance In Sramsmentioning

confidence: 99%

“…The effect is pronounced in SRAMs where minimum-geometry transistors are used. The number of variation-induced defective memory cells becomes high with device scaling [6] [2], leading the conventional redundancy techniques (e.g., using redundancy rows/columns) to become impractical. Combination of a redundancy technique with ECC can tolerate a high degree of random defects [13] [14].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

SEVA: A Soft-Error- and Variation-Aware Cache Architecture

Hung¹,

Goshima²,

Sakai³

2006

2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06)

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Section: Soft Error Tolerance In Sramsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

SEVA: A Soft-Error- and Variation-Aware Cache Architecture

Hung¹,

Goshima²,

Sakai³

2006

2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06)

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“…Recently, methods have been developed to characterize SRAM variability by measuring DC read/write/retention margins in small SRAM macros with wired-out storage nodes. In these macros SRAM is commonly characterized by measuring the I-V characteristics of its constituent transistors or by characterizing the static read stability or static writeability of the SRAM cells [35]. This method requires the insertion of large switch networks to access all internal storage nodes without changing the lithographic environment of the cells, Figure 6.…”

Section: Sram Characterizationmentioning

confidence: 99%

Technology variability from a design perspective

Nikolić

Giraud

Guo

et al. 2010

IEEE Custom Integrated Circuits Conference 2010

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Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are reviewed in this paper. Transistor and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by padded-out cells and minimum operating voltages for the entire array. Correlations between various components of variability are essential for adding appropriate margins to the design.

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“…Write margin can also be measured as the writeability current (I W , as defined in Fig. 4c and [4]), or the write noise margin derived from the butterfly curves (BFC) [1].…”

Section: Introductionmentioning

confidence: 99%

“…Write margin can also be measured as the writeability current (I W , as defined in Fig. 4c and [4]), or the write noise margin derived from the butterfly curves (BFC) [1].Read Stability: The read stability of an SRAM cell is conventionally quantified by the cell read static noise margin (RSNM) [5] and is highly sensitive to the cell supply. To characterize the read stability of an SRAM cell in a large array, BL current at the '0' storage node (I MEAS1 ) is monitored while ramping down the cell supply with the bit-lines pre-charged and WL driven by the nominal supply.…”

mentioning

confidence: 99%

Large-scale read/write margin measurement in 45nm CMOS SRAM arrays

Guo

Carlson

Pang

et al. 2008

2008 IEEE Symposium on VLSI Circuits

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Distributions of read and write noise margins in large CMOS SRAM arrays are investigated by directly measuring the bit-line current during bitline / wordline (write) or cell supply (read) voltage sweep in a 768Kb 45nm CMOS SRAM test-chip. Good correlation between write/read margin estimates through the bit-line measurements and the DC read SNM (RSNM) and I W measurements in small on-chip SRAM macros with wired-out storage nodes are demonstrated. Four common writeability metrics are correlated and compared. Array-level characterization of SRAM cell read stability and writeability allow fast and accurate characterization of highdensity SRAM arrays is scalable for capturing up to 6 standard deviations of parameter variations. Introduction Continued increase in the process variability is perceived to be a major challenge in future technology scaling. To satisfy the functionality of hundreds of millions of SRAM cells in current ondie cache memories, the design has to provide more than 6 standard deviations of margin to parameter variations. Margins have been estimated through TCAD simulations or by measuring DC read/write margins in small SRAM macros with wired-out storage nodes [1-2] and direct cell current measurement in large SRAM arrays [3]. In this work, SRAM cell read stability and writeability margins are estimated through bitline currents and compared to direct DC RSNM and I W measurements.Measurement Methodology Writeability: During a write operation, a low-going BL R voltage pulls down on the '1' storage node as the WL is held high until the trip point of the inverter formed by PR and NR is reached, and a bit cell is successfully written (Fig. 1a). In this work, the measurements of four commonly used writeability metrics are compared and correlated. The BL write margin (BLWM) is the maximum BL voltage able to flip the cell state and can be measured through monitoring the BL L current at the '0' storage (I MEAS1 in Fig. 1a) while ramping down the BL R voltage with WL held high. The voltage at BL R that induces a sudden drop in I MEAS1 is the write margin of the cell (Fig. 1b). Similarly, a WL write margin (WLWM) can be defined as the maximum of (V DD -V WL ) in a WL voltage sweep (Fig. 1c) while monitoring the change in the BL current at the '1' storage node (I MEAS2 in Fig. 1a). Write margin can also be measured as the writeability current (I W , as defined in Fig. 4c and [4]), or the write noise margin derived from the butterfly curves (BFC) [1].Read Stability: The read stability of an SRAM cell is conventionally quantified by the cell read static noise margin (RSNM) [5] and is highly sensitive to the cell supply. To characterize the read stability of an SRAM cell in a large array, BL current at the '0' storage node (I MEAS1 ) is monitored while ramping down the cell supply with the bit-lines pre-charged and WL driven by the nominal supply. The difference between the nominal supply and the cell supply causing I MEAS1 to drop gives the read margin (RM) of the SRAM cell under test (Fig. 1d).Array Imp...

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Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells

Abstract: Abstract

Cited by 141 publications

References 12 publications

SEVA: A Soft-Error- and Variation-Aware Cache Architecture

SEVA: A Soft-Error- and Variation-Aware Cache Architecture

Technology variability from a design perspective

Large-scale read/write margin measurement in 45nm CMOS SRAM arrays

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