Cross-layer routing technique interacts among the various layers of the OSI model and exchanges information among them. It enhances the usage of network resources and achieves significant performance improvements in Quality of Service (QoS) parameters. The Low Energy Adaptive Clustering Hierarchy Protocol (LEACH) routing algorithm consumes higher energy due to communication overhead and thus, a hierarchical model-based routing protocol named Cross-Layer Energy Efficient Scalable-Low Energy Adaptive Clustering Hierarchy Protocol (CLEES-LEACH) is proposed. This increases scalability using the Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA) protocol between the intermediary node and cluster head, with the overhead of latency. A Linear Programming model is used, which further makes use of scheduling to overcome latency. Energy efficiency and latency are addressed with the proposed cross-layer routing algorithm CLEES-LEACH. The cross-layer design establishes Physical, Media Access Control (MAC), and Network layer interactions in the proposed algorithm. The present LEACH algorithm also increases the network overhead as there is no mechanism for communication among the network layer and consumes high energy. In the proposed algorithm CLEES-LEACH, latency is reduced to 25% and throughput is maximized to 20% compared to existing Energy-Efficient Distributed Schedule Based protocol (EEDS) and Integer Linear Programming (ILP) protocols. The energy consumption is also reduced to 20 % and the scalability is increased to 10 % compared to the existing LEACH and CL-LEACH protocols. These results are shown by using NS3 simulation.
In this paper, we consider processors which provide an idle instruction to the user for powering down processor units which are not required during portions of program execution. We describe algorithms which can be implemented in an energy-aware compiler to make efficient use of such an instruction. These algorithms are based on program static analysis and a combinatorial optimization formulation of the problem. We assume as input an assembly language program of the processor in question. The problem is to insert the idle instruction at different places in the assembly language program such that energy saving is maximized and the execution time of the resulting program is not increased beyond a user-specified value. * This work was done at Sasken Communication Technolo-
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