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This work presents a new fast model, based on piecewise linear (PWL) methodology, for pseudo-resistors SPICE simulation, including the non-linear working range, fully supported by experimental data. SPICE simulations with fixed resistances or transistor modelled as pseudoresistors do not reproduce simultaneously its real behavior for both the linear and the non-linear regions. A complete set of steps which validate the PWL macromodel for bio-amplifiers project is presented. As a case study, this paper addresses the pseudo-resistor characteristics operating in the non-linear region when implemented in a low-frequency bio-potential amplifier with narrow bandwidth, for use in heart rate meters and QRS complex monitoring systems. The use of the pseudo-resistor in this low-voltage low-power topology associates DC offset cancellation with an adequate frequency response. Moreover, this work shows that the non-linear characteristics of these devices can be used for a significant reduction in bio-amplifier recovery time (a.k.a. settling time) without any additional device or mechanism, making the heart rate measurements steadier and more reliable than obtained so far in current systems. The transient recovery time, as well as the response to QRS complex, was widely evaluated through experimental measurements and SPICE simulations, thanks to the proposed model. The bio-potential amplifier design was implemented using GF 8HP 0.13 μm BiCMOS technology from Global Foundries. Keywords: piecewise linear macro-model, MOS bipolar pseudo-resistor, pseudo-resistor, small recovery time, bio-potential amplifier, low power design

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (A V ), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

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The strained silicon technology together to the reduction of the temperature is studied in this paper on trapezoidal triple gate FinFETs, through three-dimensional numerical simulation, with particular focus on analog parameters. The comparison of the intrinsic voltage gain between the different trapezoidal fin shapes demonstrated that, although the strained silicon technology provided higher intrinsic voltage gain, the fin shape can have a major role in analog parameters, helping to improve those parameters under certain circumstances. Higher intrinsic voltage gains were obtained for strained devices with top fin width larger than bottom.